github-mirror/sa2
1
0 Fork 0
mirror of https://github.com/SAT-R/sa2.git synced 2026-10-28 09:43:38 +00:00
Code Issues Packages Projects Releases Wiki Activity

start decompiling multi_sio

Browse Source
This commit is contained in:
Oliver Bell committed 2022-04-06 10:25:16 +08:00
1 parent 5aecbf282f
commit 37cc81e813
18 files changed
+1009 -798
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

asm/code0.s
+1 -1
View File
@@ -1,5 +1,5 @@
.include "asm/macros.inc"
.include "include/gba.inc"
.include "constants/constants.inc"
.syntax unified
.arm
asm/code1.s
+1 -1
View File
@@ -1,5 +1,5 @@
.include "asm/macros.inc"
.include "include/gba.inc"
.include "constants/constants.inc"
.syntax unified
.arm
asm/code2.s
+1 -1
View File
@@ -1,5 +1,5 @@
.include "asm/macros.inc"
.include "include/gba.inc"
.include "constants/constants.inc"
.syntax unified
.arm
asm/crt0.s
+1 -1
View File
@@ -1,5 +1,5 @@
.include "asm/macros.inc"
.include "include/gba.inc"
.include "constants/constants.inc"
.syntax unified
.arm
asm/libagbsyscall.s
+1 -1
View File
@@ -1,5 +1,5 @@
.include "asm/macros.inc"
.include "include/gba.inc"
.include "constants/constants.inc"
.syntax unified
.arm
asm/libraries.s → asm/libraries1.s
+17 -230
View File
@@ -1,222 +1,9 @@
.include "asm/macros.inc"
.include "include/gba.inc"
.include "constants/constants.inc"
.syntax unified
.arm
arm_func_start sub_80001CC
sub_80001CC: @ 0x080001CC
push {r4, r5, r6, r7, r8, sb, sl, fp}
mov ip, #0x4000000
ldr fp, _08000208 @ =gUnknown_03000560
add sl, fp, #0x40
mov sb, #1
mov r8, #0
strb r8, [ip, #0x208]
ldm sl, {r0, r1, r2, r3, r4, r5, r6, r7}
stm sl!, {r4, r5, r6, r7}
stm sl!, {r0, r1, r2, r3}
ldr r0, [fp, #4]
str r8, [fp, #4]
strb sb, [ip, #0x208]
pop {r4, r5, r6, r7, r8, sb, sl, fp}
bx lr
.align 2, 0
_08000208: .4byte gUnknown_03000560
arm_func_start sub_800020C
sub_800020C: @ 0x0800020C
mov ip, #0x4000000
add ip, ip, #0x120
ldm ip, {r0, r1}
push {r7, r8, sb, sl, fp}
ldr fp, _08000324 @ =gUnknown_03000560
mov sb, #0xfe
add sb, sb, #0xfe00
ldrh r3, [ip, #8]
and r3, r3, #0x40
strb r3, [fp, #9]
ldr sl, [fp, #0x14]
adds r3, sl, #1
blt _08000268
bne _0800025C
strh sb, [ip, #0xa]
add r8, fp, #0x28
ldm r8, {r2, r3}
mov r7, r2
stm r8, {r3, r7}
b _08000268
_0800025C:
ldr r3, [fp, #0x2c]
ldr r2, [r3, sl, lsl #1]
strh r2, [ip, #0xa]
_08000268:
cmp sl, #0xd
addlt sl, sl, #1
strlt sl, [fp, #0x14]
push {r0, r1, r5, r6}
mov r6, #3
_0800027C:
add r8, fp, #0x18
add r8, r8, r6, lsl #2
ldr sl, [r8]
lsl r3, r6, #1
ldrh r5, [sp, r3]
cmp r5, sb
bne _080002AC
cmp sl, #0xb
ble _080002AC
mov r0, #1
sub sl, r0, #2
b _080002D8
_080002AC:
ldr r0, [r8, #0x18]
lsl r3, sl, #1
strh r5, [r0, r3]
cmp sl, #0xb
bne _080002D8
ldr r1, [r8, #0x28]
str r0, [r8, #0x28]
str r1, [r8, #0x18]
add r3, fp, #4
mov r0, #1
strb r0, [r3, r6]
_080002D8:
cmp sl, #0xd
addlt sl, sl, #1
str sl, [r8]
subs r6, r6, #1
bge _0800027C
ldrb r0, [fp]
cmp r0, #0
beq _08000318
ldr r7, _08000328 @ =0x0400010E
mov r0, #0
strh r0, [r7]
ldrh r0, [ip, #8]
orr r0, r0, #0x80
strh r0, [ip, #8]
mov r0, #0xc0
strh r0, [r7]
_08000318:
add sp, sp, #8
pop {r5, r6, r7, r8, sb, sl, fp}
bx lr
.align 2, 0
_08000324: .4byte gUnknown_03000560
_08000328: .4byte 0x0400010E
thumb_func_start MultiSioInit
MultiSioInit: @ 0x0800032C
push {r4, r5, r6, r7, lr}
sub sp, #4
adds r5, r0, #0
ldr r3, _080003EC @ =0x04000208
movs r4, #0
strh r4, [r3]
ldr r2, _080003F0 @ =0x04000200
ldrh r1, [r2]
ldr r0, _080003F4 @ =0x0000FF3F
ands r0, r1
strh r0, [r2]
movs r0, #1
strh r0, [r3]
ldr r0, _080003F8 @ =0x04000134
strh r4, [r0]
subs r2, #0xd8
movs r0, #0x80
lsls r0, r0, #6
str r0, [r2]
ldrh r0, [r2]
ldr r3, _080003FC @ =0x00004003
adds r1, r3, #0
orrs r0, r1
strh r0, [r2]
movs r0, #0
str r0, [sp]
ldr r4, _08000400 @ =gUnknown_03000560
ldr r2, _08000404 @ =0x0500007A
mov r0, sp
adds r1, r4, #0
bl CpuSet
ldr r0, _08000408 @ =sub_80001CC
ldr r1, _0800040C @ =gUnknown_03000750
ldr r2, _08000410 @ =0x04000010
bl CpuSet
ldr r0, _08000414 @ =sub_800020C
ldr r1, _08000418 @ =gMultiSioIntrFuncBuf
ldr r2, _0800041C @ =0x04000048
bl CpuSet
strb r5, [r4, #2]
movs r0, #0xd
str r0, [r4, #0x14]
adds r0, r4, #0
adds r0, #0x60
str r0, [r4, #0x28]
adds r0, #0x1c
str r0, [r4, #0x2c]
movs r3, #0
adds r2, r4, #0
movs r0, #0x30
adds r0, r0, r2
mov ip, r0
adds r6, r2, #0
adds r6, #0xd0
adds r7, r2, #0
adds r7, #0x40
adds r5, r2, #0
adds r5, #0x98
movs r4, #0
_080003A8:
lsls r0, r3, #2
mov r1, ip
adds r1, #4
mov ip, r1
subs r1, #4
stm r1!, {r5}
adds r1, r2, #0
adds r1, #0xb4
adds r1, r4, r1
stm r7!, {r1}
adds r1, r2, #0
adds r1, #0x50
adds r0, r0, r1
str r6, [r0]
adds r6, #0x54
adds r5, #0x54
adds r4, #0x54
adds r3, #1
cmp r3, #3
ble _080003A8
ldr r3, _080003EC @ =0x04000208
movs r0, #0
strh r0, [r3]
ldr r2, _080003F0 @ =0x04000200
ldrh r0, [r2]
movs r1, #0x80
orrs r0, r1
strh r0, [r2]
movs r0, #1
strh r0, [r3]
add sp, #4
pop {r4, r5, r6, r7}
pop {r0}
bx r0
.align 2, 0
_080003EC: .4byte 0x04000208
_080003F0: .4byte 0x04000200
_080003F4: .4byte 0x0000FF3F
_080003F8: .4byte 0x04000134
_080003FC: .4byte 0x00004003
_08000400: .4byte gUnknown_03000560
_08000404: .4byte 0x0500007A
_08000408: .4byte sub_80001CC
_0800040C: .4byte gUnknown_03000750
_08000410: .4byte 0x04000010
_08000414: .4byte sub_800020C
_08000418: .4byte gMultiSioIntrFuncBuf
_0800041C: .4byte 0x04000048
thumb_func_start MultiSioMain
MultiSioMain: @ 0x08000420
push {r4, r5, r6, r7, lr}
@@ -228,7 +15,7 @@ MultiSioMain: @ 0x08000420
mov r8, r2
ldr r5, _08000440 @ =0x04000128
ldr r6, [r5]
ldr r7, _08000444 @ =gUnknown_03000560
ldr r7, _08000444 @ =gMultiSioArea
ldrb r0, [r7, #1]
cmp r0, #0
beq _08000448
@@ -237,7 +24,7 @@ MultiSioMain: @ 0x08000420
b _080004BE
.align 2, 0
_08000440: .4byte 0x04000128
_08000444: .4byte gUnknown_03000560
_08000444: .4byte gMultiSioArea
_08000448:
movs r1, #0x30
adds r0, r6, #0
@@ -289,7 +76,7 @@ _08000448:
orrs r0, r1
strb r0, [r5]
_080004AA:
ldr r1, _08000504 @ =gUnknown_03000560
ldr r1, _08000504 @ =gMultiSioArea
movs r0, #1
strb r0, [r1, #1]
_080004B0:
@@ -299,7 +86,7 @@ _080004B0:
mov r1, r8
bl sub_8000538
_080004BE:
ldr r1, _08000504 @ =gUnknown_03000560
ldr r1, _08000504 @ =gMultiSioArea
ldrb r0, [r1, #0xb]
adds r0, #1
strb r0, [r1, #0xb]
@@ -329,7 +116,7 @@ _080004F4: .4byte 0x04000200
_080004F8: .4byte 0x0000FF7F
_080004FC: .4byte 0x04000202
_08000500: .4byte 0x0000BBBC
_08000504: .4byte gUnknown_03000560
_08000504: .4byte gMultiSioArea
_08000508:
adds r0, r3, #0
orrs r0, r2
@@ -363,7 +150,7 @@ _0800052A:
sub_8000538: @ 0x08000538
push {r4, r5, r6, r7, lr}
movs r7, #0
ldr r5, _080005F8 @ =gUnknown_03000560
ldr r5, _080005F8 @ =gMultiSioArea
ldr r4, [r5, #0x28]
movs r2, #1
ands r1, r2
@@ -459,7 +246,7 @@ _080005F0:
pop {r0}
bx r0
.align 2, 0
_080005F8: .4byte gUnknown_03000560
_080005F8: .4byte gMultiSioArea
_080005FC: .4byte gUnknown_03000790
_08000600: .4byte 0x04000005
_08000604: .4byte 0x0400010E
@@ -473,12 +260,12 @@ sub_8000608: @ 0x08000608
push {r5, r6, r7}
sub sp, #0x14
str r0, [sp, #0xc]
ldr r0, _08000714 @ =gUnknown_03000750
ldr r0, _08000714 @ =gMultiSioRecvFuncBuf
movs r4, #0
str r4, [sp]
bl _call_via_r0
str r0, [sp, #4]
ldr r0, _08000718 @ =gUnknown_03000560
ldr r0, _08000718 @ =gMultiSioArea
strb r4, [r0, #3]
add r1, sp, #4
mov sl, r1
@@ -560,7 +347,7 @@ _080006AA:
ldr r4, [sp, #0x10]
cmp r4, #3
ble _08000638
ldr r0, _08000718 @ =gUnknown_03000560
ldr r0, _08000718 @ =gMultiSioArea
ldrb r1, [r0, #2]
ldrb r2, [r0, #3]
adds r3, r1, #0
@@ -601,8 +388,8 @@ _080006F8:
orrs r0, r4
b _08000742
.align 2, 0
_08000714: .4byte gUnknown_03000750
_08000718: .4byte gUnknown_03000560
_08000714: .4byte gMultiSioRecvFuncBuf
_08000718: .4byte gMultiSioArea
_0800071C: .4byte 0x04000005
_08000720: .4byte 0x05000005
_08000724:
@@ -653,7 +440,7 @@ _08000760:
thumb_func_start sub_8000774
sub_8000774: @ 0x08000774
push {lr}
ldr r2, _0800078C @ =gUnknown_03000560
ldr r2, _0800078C @ =gMultiSioArea
ldrb r0, [r2]
cmp r0, #0
beq _08000786
@@ -665,7 +452,7 @@ _08000786:
pop {r0}
bx r0
.align 2, 0
_0800078C: .4byte gUnknown_03000560
_0800078C: .4byte gMultiSioArea
thumb_func_start sub_8000790
sub_8000790: @ 0x08000790
@@ -689,7 +476,7 @@ sub_8000790: @ 0x08000790
adds r1, #0xf6
movs r0, #0xc0
strh r0, [r1]
ldr r2, _080007DC @ =gUnknown_03000560
ldr r2, _080007DC @ =gMultiSioArea
ldrb r1, [r2, #8]
movs r0, #0x7f
ands r0, r1
@@ -702,7 +489,7 @@ _080007CC: .4byte 0x0000FF3F
_080007D0: .4byte 0x04000128
_080007D4: .4byte 0x00002003
_080007D8: .4byte 0x0000BBBC
_080007DC: .4byte gUnknown_03000560
_080007DC: .4byte gMultiSioArea
thumb_func_start sub_80007E0
sub_80007E0: @ 0x080007E0
asm/m4a0.s
+1 -1
View File
@@ -1,5 +1,5 @@
.include "asm/macros.inc"
.include "include/gba.inc"
.include "constants/constants.inc"
.syntax unified
.arm
asm/multi_sio_asm.s
+222
View File
@@ -0,0 +1,222 @@
.include "asm/macros.inc"
.include "constants/constants.inc"
.syntax unified
.text
.ifdef MULTI_SIO_DI_FUNC_FAST
@--------------------------------------------------------------------
@- Update Receive Data/Check Buffer Routine -
@--------------------------------------------------------------------
arm_func_start MultiSioRecvBufChange
MultiSioRecvBufChange: @ 0x08158F14
stmfd sp!, {r4-r11}
mov r12, #REG_BASE @ r12: REG_BASE
ldr r11, =gMultiSioArea @ r11: &gMultiSioArea
add r10, r11, #OFS_MS_LAST_RECV_BUF_P @ r10: &gMultiSioArea.lastRecvBufp[0]
mov r9, #1 @ r9: 1
mov r8, #0 @ r8: 0
@ *(vu8 *)REG_ADDR_IME = 0 Disable Interrupt (29 Clocks)
strb r8, [r12, #OFFSET_REG_IME]
@ gMultiSioArea.recvCheckBufp[i] <--> gMultiSioArea.lastRecvBufp[i] Update Receive Buffer
ldmia r10, {r0-r7}
stmia r10!, {r4-r7}
stmia r10!, {r0-r3}
@ syncRecvFlagBak[i] = gMultiSioArea.syncRecvFlag[i]
@ gMultiSioArea.syncRecvFlag[i] = 0
ldr r0, [r11, #OFS_MS_SYNC_RECV_FLAG]
str r8, [r11, #OFS_MS_SYNC_RECV_FLAG]
@ *(vu8 *)REG_IME = 1 Enable Interrupt
strb r9, [r12, #OFFSET_REG_IME]
@ return gMultiSioArea.syncRecvFlag[i]
ldmfd sp!, {r4-r11}
bx lr
.ltorg
arm_func_end MultiSioRecvBufChange
@--------------------------------------------------------------------
@- Multi-play Interrupt Routine -
@--------------------------------------------------------------------
arm_func_start MultiSioIntr
MultiSioIntr: @ 0x08158F54
@ Save Receive Data
@ *(u64 *)recvTmp = *(u64 *)REG_ADDR_SIOMLT_RECV
mov r12, #REG_BASE @ r12: REG_SIOMLT_RECV
add r12, r12, #OFFSET_REG_SIOMLT_RECV
ldmia r12, {r0-r1}
@ Save Register to Stack
stmfd sp!, {r7-r11}
ldr r11, =gMultiSioArea @ r11: &gMultiSioArea
mov r9, #MULTI_SIO_SYNC_DATA & 0x00ff @ r9: MULTI_SIO_SYNC_DATA
add r9, r9, #MULTI_SIO_SYNC_DATA & 0xff00
@ Detect hard error
@ gMultiSioArea.error = REG_SIOCNT->Error
ldrh r3, [r12, #REG_SIOCNT - REG_SIOMLT_RECV]
and r3, r3, #SIO_ERROR
strb r3, [r11, #OFS_MS_HARD_ERROR]
@ Send Data Processing
@ if (gMultiSioArea.sendBufCounter == -1) {
ldr r10, [r11, #OFS_MS_SEND_BUF_COUNTER] @ r10: gMultiSioArea.sendBufCounter
adds r3, r10, #1
blt 3f
bne 2f
@ REG_SIOCNT->data = MULTI_SIO_SYNC_DATA Set Synchronization Data
strh r9, [r12, #REG_SIOMLT_SEND - REG_SIOMLT_RECV]
@ gMultiSioArea.currentSendBufp <--> gMultiSioArea.nextSendBufp Change Send Buffer
add r8, r11, #OFS_MS_NEXT_SEND_BUF_P
ldmia r8, {r2,r3}
mov r7, r2
stmia r8, {r3,r7}
b 3f
2:
@ } else if (gMultiSioArea.sendBufCounter >= 0) {
@ REG_SIOCNT->data = gMultiSioArea.currentSendBufp[gMultiSioArea.sendBufCounter]
@ Set Send Data
ldr r3, [r11, #OFS_MS_CURRENT_SEND_BUF_P]
ldr r2, [r3, r10, lsl #1]
strh r2, [r12, #REG_SIOMLT_SEND - REG_SIOMLT_RECV]
3:
@ }
@ if (gMultiSioArea.sendBufCounter < sizeof(struct MultiSioPacket) / 2 - 1)
@ gMultiSioArea.sendBufCounter++;
cmp r10, #MULTI_SIO_PACKET_SIZE / 2 - 1
addlt r10, r10, #1
strlt r10, [r11, #OFS_MS_SEND_BUF_COUNTER]
@ Save Receive Data & Register to Stack
stmfd sp!, {r0-r1, r5-r6}
@ Receive Data Processing (Max. Approx. 160 Clocks/Included in Wait Period)
@ for (i = 0; i < MULTI_SIO_PLAYERS_MAX; i++) {
mov r6, #MULTI_SIO_PLAYERS_MAX - 1 @ r6: i
4:
add r8, r11, #OFS_MS_RECV_BUF_COUNTER @ r8: &gMultiSioArea.recvBufCounter[i]
add r8, r8, r6, lsl #2
ldr r10, [r8, #0] @ r10: gMultiSioArea.recvBufCounter[i]
mov r3, r6, lsl #1 @ r5: RecvTmp[i]
ldrh r5, [sp, r3]
@ if ( recvTmp[i] == MULTI_SIO_SYNC_DATA
@ && gMultiSioArea.recvBufCounter[i] > sizeof(struct MultiSioPacket) / 2 - 3) {
cmp r5, r9
bne 6f
cmp r10, #MULTI_SIO_PACKET_SIZE / 2 - 3
ble 6f
@ gMultiSioArea.recvBufCounter[i] = -1
mov r0, #1
sub r10, r0, #2
b 7f
6:
@ } else {
@ gMultiSioArea.currentRecvBufp[i][gMultiSioArea.recvBufCounter[i]] = recvTmp[i]
@ Store Receive Data
ldr r0, [r8, #OFS_MS_CURRENT_RECV_BUF_P - OFS_MS_RECV_BUF_COUNTER]
mov r3, r10, lsl #1
strh r5, [r0, r3]
@ if (gMultiSioArea.recvBufCounter[i] == sizeof(struct MultiSioPacket) / 2 - 3)
cmp r10, #MULTI_SIO_PACKET_SIZE / 2 - 3
bne 7f
@ gMultiSioArea.currentRecvBufp[i] <--> gMultiSioArea.lastRecvBufp[i] Change Receive Buffer
ldr r1, [r8, #OFS_MS_LAST_RECV_BUF_P - OFS_MS_RECV_BUF_COUNTER]
str r0, [r8, #OFS_MS_LAST_RECV_BUF_P - OFS_MS_RECV_BUF_COUNTER]
str r1, [r8, #OFS_MS_CURRENT_RECV_BUF_P - OFS_MS_RECV_BUF_COUNTER]
@ gMultiSioArea.syncRecvFlag[i] = 1; Receive Completion Flag
add r3, r11, #OFS_MS_SYNC_RECV_FLAG
mov r0, #1
strb r0, [r3, r6]
7:
@ }
@ if (gMultiSioArea.recvBufCounter[i] < sizeof(struct MultiSioPacket) / 2 - 1)
@ gMultiSioArea.recvBufCounter[i]++;
cmp r10, #MULTI_SIO_PACKET_SIZE / 2 - 1
addlt r10, r10, #1
str r10, [r8, #0]
subs r6, r6, #1
bge 4b
@ }
@ Start Master Send
@ if (gMultiSioArea.type == SIO_MULTI_PARENT)
ldrb r0, [r11,#OFS_MS_TYPE]
cmp r0, #0
beq 11f
@ *(vu16 *)REG_ADDR_MULTI_SIO_TIMER_H = 0; Stop Timer
ldr r7, =REG_MULTI_SIO_TIMER_H @ r7: REG_MULTI_SIO_TIMER_H
mov r0, #0
strh r0, [r7, #0]
@ REG_SIOCNT |= SIO_ENABLE; Restart Send
ldrh r0, [r12, #REG_SIOCNT - REG_SIOMLT_RECV]
orr r0, r0, #SIO_ENABLE
strh r0, [r12, #REG_SIOCNT - REG_SIOMLT_RECV]
@ *(vu16 *)REG_ADDR_MULTI_SIO_TIMER_H Restart Timer
@ = (TIMER_1CLK | TIMER_INTR_ENABLE | TIMER_ENABLE);
mov r0, #0xC0
strh r0, [r7, #0]
11:
add sp, sp, #8
ldmfd sp!, {r5-r11}
bx lr
arm_func_end MultiSioIntr
.endif
constants/constants.inc
+3
View File
@@ -0,0 +1,3 @@
.include "constants/gba_constants.inc"
.include "constants/misc_constants.inc"
.include "constants/multi_sio_constants.inc"
constants/gba_constants.inc
+495
View File
@@ -0,0 +1,495 @@
.set PSR_USR_MODE, 0x00000010
.set PSR_FIQ_MODE, 0x00000011
.set PSR_IRQ_MODE, 0x00000012
.set PSR_SVC_MODE, 0x00000013
.set PSR_ABT_MODE, 0x00000017
.set PSR_UND_MODE, 0x0000001b
.set PSR_SYS_MODE, 0x0000001f
.set PSR_MODE_MASK, 0x0000001f
.set PSR_T_BIT, 0x00000020
.set PSR_F_BIT, 0x00000040
.set PSR_I_BIT, 0x00000080
.set EWRAM_START, 0x2000000
.set EWRAM_END, EWRAM_START + 0x40000
.set IWRAM_START, 0x3000000
.set IWRAM_END, IWRAM_START + 0x8000
.set PLTT, 0x5000000
.set BG_PLTT, PLTT
.set OBJ_PLTT, PLTT + 0x200
.set VRAM, 0x6000000
.set BG_VRAM, VRAM
.set OBJ_VRAM0, VRAM + 0x10000 @ text-mode BG
.set OBJ_VRAM1, VRAM + 0x14000 @ bitmap-mode BG
.set OAM, 0x7000000
.set SOUND_INFO_PTR, 0x3007FF0
.set INTR_CHECK, 0x3007FF8
.set INTR_VECTOR, 0x3007FFC
.set INTR_FLAG_VBLANK, 1 << 0
.set INTR_FLAG_HBLANK, 1 << 1
.set INTR_FLAG_VCOUNT, 1 << 2
.set INTR_FLAG_TIMER0, 1 << 3
.set INTR_FLAG_TIMER1, 1 << 4
.set INTR_FLAG_TIMER2, 1 << 5
.set INTR_FLAG_TIMER3, 1 << 6
.set INTR_FLAG_SERIAL, 1 << 7
.set INTR_FLAG_DMA0, 1 << 8
.set INTR_FLAG_DMA1, 1 << 9
.set INTR_FLAG_DMA2, 1 << 10
.set INTR_FLAG_DMA3, 1 << 11
.set INTR_FLAG_KEYPAD, 1 << 12
.set INTR_FLAG_GAMEPAK, 1 << 13
.set VCOUNT_VBLANK, 160
.set TOTAL_SCANLINES, 228
.set REG_BASE, 0x4000000 @ I/O register base address
@ I/O register offsets
.set OFFSET_REG_DISPCNT, 0x0
.set OFFSET_REG_DISPSTAT, 0x4
.set OFFSET_REG_VCOUNT, 0x6
.set OFFSET_REG_BG0CNT, 0x8
.set OFFSET_REG_BG1CNT, 0xa
.set OFFSET_REG_BG2CNT, 0xc
.set OFFSET_REG_BG3CNT, 0xe
.set OFFSET_REG_BG0HOFS, 0x10
.set OFFSET_REG_BG0VOFS, 0x12
.set OFFSET_REG_BG1HOFS, 0x14
.set OFFSET_REG_BG1VOFS, 0x16
.set OFFSET_REG_BG2HOFS, 0x18
.set OFFSET_REG_BG2VOFS, 0x1a
.set OFFSET_REG_BG3HOFS, 0x1c
.set OFFSET_REG_BG3VOFS, 0x1e
.set OFFSET_REG_BG2PA, 0x20
.set OFFSET_REG_BG2PB, 0x22
.set OFFSET_REG_BG2PC, 0x24
.set OFFSET_REG_BG2PD, 0x26
.set OFFSET_REG_BG2X_L, 0x28
.set OFFSET_REG_BG2X_H, 0x2a
.set OFFSET_REG_BG2Y_L, 0x2c
.set OFFSET_REG_BG2Y_H, 0x2e
.set OFFSET_REG_BG3PA, 0x30
.set OFFSET_REG_BG3PB, 0x32
.set OFFSET_REG_BG3PC, 0x34
.set OFFSET_REG_BG3PD, 0x36
.set OFFSET_REG_BG3X_L, 0x38
.set OFFSET_REG_BG3X_H, 0x3a
.set OFFSET_REG_BG3Y_L, 0x3c
.set OFFSET_REG_BG3Y_H, 0x3e
.set OFFSET_REG_WIN0H, 0x40
.set OFFSET_REG_WIN1H, 0x42
.set OFFSET_REG_WIN0V, 0x44
.set OFFSET_REG_WIN1V, 0x46
.set OFFSET_REG_WININ, 0x48
.set OFFSET_REG_WINOUT, 0x4a
.set OFFSET_REG_MOSAIC, 0x4c
.set OFFSET_REG_BLDCNT, 0x50
.set OFFSET_REG_BLDALPHA, 0x52
.set OFFSET_REG_BLDY, 0x54
.set OFFSET_REG_SOUND1CNT, 0x60
.set OFFSET_REG_SOUND1CNT_L, 0x60
.set OFFSET_REG_NR10, 0x60
.set OFFSET_REG_SOUND1CNT_H, 0x62
.set OFFSET_REG_NR11, 0x62
.set OFFSET_REG_NR12, 0x63
.set OFFSET_REG_SOUND1CNT_X, 0x64
.set OFFSET_REG_NR13, 0x64
.set OFFSET_REG_NR14, 0x65
.set OFFSET_REG_SOUND2CNT, 0x68
.set OFFSET_REG_SOUND2CNT_L, 0x68
.set OFFSET_REG_NR21, 0x68
.set OFFSET_REG_NR22, 0x69
.set OFFSET_REG_SOUND2CNT_H, 0x6c
.set OFFSET_REG_NR23, 0x6c
.set OFFSET_REG_NR24, 0x6d
.set OFFSET_REG_SOUND3CNT, 0x70
.set OFFSET_REG_SOUND3CNT_L, 0x70
.set OFFSET_REG_NR30, 0x70
.set OFFSET_REG_SOUND3CNT_H, 0x72
.set OFFSET_REG_NR31, 0x72
.set OFFSET_REG_NR32, 0x73
.set OFFSET_REG_SOUND3CNT_X, 0x74
.set OFFSET_REG_NR33, 0x74
.set OFFSET_REG_NR34, 0x75
.set OFFSET_REG_SOUND4CNT, 0x78
.set OFFSET_REG_SOUND4CNT_L, 0x78
.set OFFSET_REG_NR41, 0x78
.set OFFSET_REG_NR42, 0x79
.set OFFSET_REG_SOUND4CNT_H, 0x7c
.set OFFSET_REG_NR43, 0x7c
.set OFFSET_REG_NR44, 0x7d
.set OFFSET_REG_SOUNDCNT, 0x80
.set OFFSET_REG_SOUNDCNT_L, 0x80
.set OFFSET_REG_NR50, 0x80
.set OFFSET_REG_NR51, 0x81
.set OFFSET_REG_SOUNDCNT_H, 0x82
.set OFFSET_REG_SOUNDCNT_X, 0x84
.set OFFSET_REG_NR52, 0x84
.set OFFSET_REG_SOUNDBIAS, 0x88
.set OFFSET_REG_WAVE_RAM, 0x90
.set OFFSET_REG_WAVE_RAM0, 0x90
.set OFFSET_REG_WAVE_RAM0_L, 0x90
.set OFFSET_REG_WAVE_RAM0_H, 0x92
.set OFFSET_REG_WAVE_RAM1, 0x94
.set OFFSET_REG_WAVE_RAM1_L, 0x94
.set OFFSET_REG_WAVE_RAM1_H, 0x96
.set OFFSET_REG_WAVE_RAM2, 0x98
.set OFFSET_REG_WAVE_RAM2_L, 0x98
.set OFFSET_REG_WAVE_RAM2_H, 0x9a
.set OFFSET_REG_WAVE_RAM3, 0x9c
.set OFFSET_REG_WAVE_RAM3_L, 0x9c
.set OFFSET_REG_WAVE_RAM3_H, 0x9e
.set OFFSET_REG_FIFO, 0xa0
.set OFFSET_REG_FIFO_A, 0xa0
.set OFFSET_REG_FIFO_A_L, 0xa0
.set OFFSET_REG_FIFO_A_H, 0xa2
.set OFFSET_REG_FIFO_B, 0xa4
.set OFFSET_REG_FIFO_B_L, 0xa4
.set OFFSET_REG_FIFO_B_H, 0xa6
.set OFFSET_REG_DMA0, 0xb0
.set OFFSET_REG_DMA0SAD, 0xb0
.set OFFSET_REG_DMA0SAD_L, 0xb0
.set OFFSET_REG_DMA0SAD_H, 0xb2
.set OFFSET_REG_DMA0DAD, 0xb4
.set OFFSET_REG_DMA0DAD_L, 0xb4
.set OFFSET_REG_DMA0DAD_H, 0xb6
.set OFFSET_REG_DMA0CNT, 0xb8
.set OFFSET_REG_DMA0CNT_L, 0xb8
.set OFFSET_REG_DMA0CNT_H, 0xba
.set OFFSET_REG_DMA1, 0xbc
.set OFFSET_REG_DMA1SAD, 0xbc
.set OFFSET_REG_DMA1SAD_L, 0xbc
.set OFFSET_REG_DMA1SAD_H, 0xbe
.set OFFSET_REG_DMA1DAD, 0xc0
.set OFFSET_REG_DMA1DAD_L, 0xc0
.set OFFSET_REG_DMA1DAD_H, 0xc2
.set OFFSET_REG_DMA1CNT, 0xc4
.set OFFSET_REG_DMA1CNT_L, 0xc4
.set OFFSET_REG_DMA1CNT_H, 0xc6
.set OFFSET_REG_DMA2, 0xc8
.set OFFSET_REG_DMA2SAD, 0xc8
.set OFFSET_REG_DMA2SAD_L, 0xc8
.set OFFSET_REG_DMA2SAD_H, 0xca
.set OFFSET_REG_DMA2DAD, 0xcc
.set OFFSET_REG_DMA2DAD_L, 0xcc
.set OFFSET_REG_DMA2DAD_H, 0xce
.set OFFSET_REG_DMA2CNT, 0xd0
.set OFFSET_REG_DMA2CNT_L, 0xd0
.set OFFSET_REG_DMA2CNT_H, 0xd2
.set OFFSET_REG_DMA3, 0xd4
.set OFFSET_REG_DMA3SAD, 0xd4
.set OFFSET_REG_DMA3SAD_L, 0xd4
.set OFFSET_REG_DMA3SAD_H, 0xd6
.set OFFSET_REG_DMA3DAD, 0xd8
.set OFFSET_REG_DMA3DAD_L, 0xd8
.set OFFSET_REG_DMA3DAD_H, 0xda
.set OFFSET_REG_DMA3CNT, 0xdc
.set OFFSET_REG_DMA3CNT_L, 0xdc
.set OFFSET_REG_DMA3CNT_H, 0xde
.set OFFSET_REG_TM0CNT, 0x100
.set OFFSET_REG_TM0CNT_L, 0x100
.set OFFSET_REG_TM0CNT_H, 0x102
.set OFFSET_REG_TM1CNT, 0x104
.set OFFSET_REG_TM1CNT_L, 0x104
.set OFFSET_REG_TM1CNT_H, 0x106
.set OFFSET_REG_TM2CNT, 0x108
.set OFFSET_REG_TM2CNT_L, 0x108
.set OFFSET_REG_TM2CNT_H, 0x10a
.set OFFSET_REG_TM3CNT, 0x10c
.set OFFSET_REG_TM3CNT_L, 0x10c
.set OFFSET_REG_TM3CNT_H, 0x10e
.set OFFSET_REG_SIOCNT, 0x128
.set OFFSET_REG_SIODATA8, 0x12a
.set OFFSET_REG_SIODATA32, 0x120
.set OFFSET_REG_SIOMLT_SEND, 0x12a
.set OFFSET_REG_SIOMLT_RECV, 0x120
.set OFFSET_REG_SIOMULTI0, 0x120
.set OFFSET_REG_SIOMULTI1, 0x122
.set OFFSET_REG_SIOMULTI2, 0x124
.set OFFSET_REG_SIOMULTI3, 0x126
.set OFFSET_REG_KEYINPUT, 0x130
.set OFFSET_REG_KEYCNT, 0x132
.set OFFSET_REG_RCNT, 0x134
.set OFFSET_REG_JOYCNT, 0x140
.set OFFSET_REG_JOYSTAT, 0x158
.set OFFSET_REG_JOY_RECV, 0x150
.set OFFSET_REG_JOY_RECV_L, 0x150
.set OFFSET_REG_JOY_RECV_H, 0x152
.set OFFSET_REG_JOY_TRANS, 0x154
.set OFFSET_REG_JOY_TRANS_L, 0x154
.set OFFSET_REG_JOY_TRANS_H, 0x156
.set OFFSET_REG_IME, 0x208
.set OFFSET_REG_IE, 0x200
.set OFFSET_REG_IF, 0x202
.set OFFSET_REG_WAITCNT, 0x204
@ I/O register addresses
.set REG_DISPCNT, REG_BASE + OFFSET_REG_DISPCNT
.set REG_DISPSTAT, REG_BASE + OFFSET_REG_DISPSTAT
.set REG_VCOUNT, REG_BASE + OFFSET_REG_VCOUNT
.set REG_BG0CNT, REG_BASE + OFFSET_REG_BG0CNT
.set REG_BG1CNT, REG_BASE + OFFSET_REG_BG1CNT
.set REG_BG2CNT, REG_BASE + OFFSET_REG_BG2CNT
.set REG_BG3CNT, REG_BASE + OFFSET_REG_BG3CNT
.set REG_BG0HOFS, REG_BASE + OFFSET_REG_BG0HOFS
.set REG_BG0VOFS, REG_BASE + OFFSET_REG_BG0VOFS
.set REG_BG1HOFS, REG_BASE + OFFSET_REG_BG1HOFS
.set REG_BG1VOFS, REG_BASE + OFFSET_REG_BG1VOFS
.set REG_BG2HOFS, REG_BASE + OFFSET_REG_BG2HOFS
.set REG_BG2VOFS, REG_BASE + OFFSET_REG_BG2VOFS
.set REG_BG3HOFS, REG_BASE + OFFSET_REG_BG3HOFS
.set REG_BG3VOFS, REG_BASE + OFFSET_REG_BG3VOFS
.set REG_BG2PA, REG_BASE + OFFSET_REG_BG2PA
.set REG_BG2PB, REG_BASE + OFFSET_REG_BG2PB
.set REG_BG2PC, REG_BASE + OFFSET_REG_BG2PC
.set REG_BG2PD, REG_BASE + OFFSET_REG_BG2PD
.set REG_BG2X_L, REG_BASE + OFFSET_REG_BG2X_L
.set REG_BG2X_H, REG_BASE + OFFSET_REG_BG2X_H
.set REG_BG2Y_L, REG_BASE + OFFSET_REG_BG2Y_L
.set REG_BG2Y_H, REG_BASE + OFFSET_REG_BG2Y_H
.set REG_BG3PA, REG_BASE + OFFSET_REG_BG3PA
.set REG_BG3PB, REG_BASE + OFFSET_REG_BG3PB
.set REG_BG3PC, REG_BASE + OFFSET_REG_BG3PC
.set REG_BG3PD, REG_BASE + OFFSET_REG_BG3PD
.set REG_BG3X_L, REG_BASE + OFFSET_REG_BG3X_L
.set REG_BG3X_H, REG_BASE + OFFSET_REG_BG3X_H
.set REG_BG3Y_L, REG_BASE + OFFSET_REG_BG3Y_L
.set REG_BG3Y_H, REG_BASE + OFFSET_REG_BG3Y_H
.set REG_WIN0H, REG_BASE + OFFSET_REG_WIN0H
.set REG_WIN1H, REG_BASE + OFFSET_REG_WIN1H
.set REG_WIN0V, REG_BASE + OFFSET_REG_WIN0V
.set REG_WIN1V, REG_BASE + OFFSET_REG_WIN1V
.set REG_WININ, REG_BASE + OFFSET_REG_WININ
.set REG_WINOUT, REG_BASE + OFFSET_REG_WINOUT
.set REG_MOSAIC, REG_BASE + OFFSET_REG_MOSAIC
.set REG_BLDCNT, REG_BASE + OFFSET_REG_BLDCNT
.set REG_BLDALPHA, REG_BASE + OFFSET_REG_BLDALPHA
.set REG_BLDY, REG_BASE + OFFSET_REG_BLDY
.set REG_SOUND1CNT, REG_BASE + OFFSET_REG_SOUND1CNT
.set REG_SOUND1CNT_L, REG_BASE + OFFSET_REG_SOUND1CNT_L
.set REG_NR10, REG_BASE + OFFSET_REG_NR10
.set REG_SOUND1CNT_H, REG_BASE + OFFSET_REG_SOUND1CNT_H
.set REG_NR11, REG_BASE + OFFSET_REG_NR11
.set REG_NR12, REG_BASE + OFFSET_REG_NR12
.set REG_SOUND1CNT_X, REG_BASE + OFFSET_REG_SOUND1CNT_X
.set REG_NR13, REG_BASE + OFFSET_REG_NR13
.set REG_NR14, REG_BASE + OFFSET_REG_NR14
.set REG_SOUND2CNT, REG_BASE + OFFSET_REG_SOUND2CNT
.set REG_SOUND2CNT_L, REG_BASE + OFFSET_REG_SOUND2CNT_L
.set REG_NR21, REG_BASE + OFFSET_REG_NR21
.set REG_NR22, REG_BASE + OFFSET_REG_NR22
.set REG_SOUND2CNT_H, REG_BASE + OFFSET_REG_SOUND2CNT_H
.set REG_NR23, REG_BASE + OFFSET_REG_NR23
.set REG_NR24, REG_BASE + OFFSET_REG_NR24
.set REG_SOUND3CNT, REG_BASE + OFFSET_REG_SOUND3CNT
.set REG_SOUND3CNT_L, REG_BASE + OFFSET_REG_SOUND3CNT_L
.set REG_NR30, REG_BASE + OFFSET_REG_NR30
.set REG_SOUND3CNT_H, REG_BASE + OFFSET_REG_SOUND3CNT_H
.set REG_NR31, REG_BASE + OFFSET_REG_NR31
.set REG_NR32, REG_BASE + OFFSET_REG_NR32
.set REG_SOUND3CNT_X, REG_BASE + OFFSET_REG_SOUND3CNT_X
.set REG_NR33, REG_BASE + OFFSET_REG_NR33
.set REG_NR34, REG_BASE + OFFSET_REG_NR34
.set REG_SOUND4CNT, REG_BASE + OFFSET_REG_SOUND4CNT
.set REG_SOUND4CNT_L, REG_BASE + OFFSET_REG_SOUND4CNT_L
.set REG_NR41, REG_BASE + OFFSET_REG_NR41
.set REG_NR42, REG_BASE + OFFSET_REG_NR42
.set REG_SOUND4CNT_H, REG_BASE + OFFSET_REG_SOUND4CNT_H
.set REG_NR43, REG_BASE + OFFSET_REG_NR43
.set REG_NR44, REG_BASE + OFFSET_REG_NR44
.set REG_SOUNDCNT, REG_BASE + OFFSET_REG_SOUNDCNT
.set REG_SOUNDCNT_L, REG_BASE + OFFSET_REG_SOUNDCNT_L
.set REG_NR50, REG_BASE + OFFSET_REG_NR50
.set REG_NR51, REG_BASE + OFFSET_REG_NR51
.set REG_SOUNDCNT_H, REG_BASE + OFFSET_REG_SOUNDCNT_H
.set REG_SOUNDCNT_X, REG_BASE + OFFSET_REG_SOUNDCNT_X
.set REG_NR52, REG_BASE + OFFSET_REG_NR52
.set REG_SOUNDBIAS, REG_BASE + OFFSET_REG_SOUNDBIAS
.set REG_WAVE_RAM, REG_BASE + OFFSET_REG_WAVE_RAM
.set REG_WAVE_RAM0, REG_BASE + OFFSET_REG_WAVE_RAM0
.set REG_WAVE_RAM0_L, REG_BASE + OFFSET_REG_WAVE_RAM0_L
.set REG_WAVE_RAM0_H, REG_BASE + OFFSET_REG_WAVE_RAM0_H
.set REG_WAVE_RAM1, REG_BASE + OFFSET_REG_WAVE_RAM1
.set REG_WAVE_RAM1_L, REG_BASE + OFFSET_REG_WAVE_RAM1_L
.set REG_WAVE_RAM1_H, REG_BASE + OFFSET_REG_WAVE_RAM1_H
.set REG_WAVE_RAM2, REG_BASE + OFFSET_REG_WAVE_RAM2
.set REG_WAVE_RAM2_L, REG_BASE + OFFSET_REG_WAVE_RAM2_L
.set REG_WAVE_RAM2_H, REG_BASE + OFFSET_REG_WAVE_RAM2_H
.set REG_WAVE_RAM3, REG_BASE + OFFSET_REG_WAVE_RAM3
.set REG_WAVE_RAM3_L, REG_BASE + OFFSET_REG_WAVE_RAM3_L
.set REG_WAVE_RAM3_H, REG_BASE + OFFSET_REG_WAVE_RAM3_H
.set REG_FIFO, REG_BASE + OFFSET_REG_FIFO
.set REG_FIFO_A, REG_BASE + OFFSET_REG_FIFO_A
.set REG_FIFO_A_L, REG_BASE + OFFSET_REG_FIFO_A_L
.set REG_FIFO_A_H, REG_BASE + OFFSET_REG_FIFO_A_H
.set REG_FIFO_B, REG_BASE + OFFSET_REG_FIFO_B
.set REG_FIFO_B_L, REG_BASE + OFFSET_REG_FIFO_B_L
.set REG_FIFO_B_H, REG_BASE + OFFSET_REG_FIFO_B_H
.set REG_DMA0, REG_BASE + OFFSET_REG_DMA0
.set REG_DMA0SAD, REG_BASE + OFFSET_REG_DMA0SAD
.set REG_DMA0SAD_L, REG_BASE + OFFSET_REG_DMA0SAD_L
.set REG_DMA0SAD_H, REG_BASE + OFFSET_REG_DMA0SAD_H
.set REG_DMA0DAD, REG_BASE + OFFSET_REG_DMA0DAD
.set REG_DMA0DAD_L, REG_BASE + OFFSET_REG_DMA0DAD_L
.set REG_DMA0DAD_H, REG_BASE + OFFSET_REG_DMA0DAD_H
.set REG_DMA0CNT, REG_BASE + OFFSET_REG_DMA0CNT
.set REG_DMA0CNT_L, REG_BASE + OFFSET_REG_DMA0CNT_L
.set REG_DMA0CNT_H, REG_BASE + OFFSET_REG_DMA0CNT_H
.set REG_DMA1, REG_BASE + OFFSET_REG_DMA1
.set REG_DMA1SAD, REG_BASE + OFFSET_REG_DMA1SAD
.set REG_DMA1SAD_L, REG_BASE + OFFSET_REG_DMA1SAD_L
.set REG_DMA1SAD_H, REG_BASE + OFFSET_REG_DMA1SAD_H
.set REG_DMA1DAD, REG_BASE + OFFSET_REG_DMA1DAD
.set REG_DMA1DAD_L, REG_BASE + OFFSET_REG_DMA1DAD_L
.set REG_DMA1DAD_H, REG_BASE + OFFSET_REG_DMA1DAD_H
.set REG_DMA1CNT, REG_BASE + OFFSET_REG_DMA1CNT
.set REG_DMA1CNT_L, REG_BASE + OFFSET_REG_DMA1CNT_L
.set REG_DMA1CNT_H, REG_BASE + OFFSET_REG_DMA1CNT_H
.set REG_DMA2, REG_BASE + OFFSET_REG_DMA2
.set REG_DMA2SAD, REG_BASE + OFFSET_REG_DMA2SAD
.set REG_DMA2SAD_L, REG_BASE + OFFSET_REG_DMA2SAD_L
.set REG_DMA2SAD_H, REG_BASE + OFFSET_REG_DMA2SAD_H
.set REG_DMA2DAD, REG_BASE + OFFSET_REG_DMA2DAD
.set REG_DMA2DAD_L, REG_BASE + OFFSET_REG_DMA2DAD_L
.set REG_DMA2DAD_H, REG_BASE + OFFSET_REG_DMA2DAD_H
.set REG_DMA2CNT, REG_BASE + OFFSET_REG_DMA2CNT
.set REG_DMA2CNT_L, REG_BASE + OFFSET_REG_DMA2CNT_L
.set REG_DMA2CNT_H, REG_BASE + OFFSET_REG_DMA2CNT_H
.set REG_DMA3, REG_BASE + OFFSET_REG_DMA3
.set REG_DMA3SAD, REG_BASE + OFFSET_REG_DMA3SAD
.set REG_DMA3SAD_L, REG_BASE + OFFSET_REG_DMA3SAD_L
.set REG_DMA3SAD_H, REG_BASE + OFFSET_REG_DMA3SAD_H
.set REG_DMA3DAD, REG_BASE + OFFSET_REG_DMA3DAD
.set REG_DMA3DAD_L, REG_BASE + OFFSET_REG_DMA3DAD_L
.set REG_DMA3DAD_H, REG_BASE + OFFSET_REG_DMA3DAD_H
.set REG_DMA3CNT, REG_BASE + OFFSET_REG_DMA3CNT
.set REG_DMA3CNT_L, REG_BASE + OFFSET_REG_DMA3CNT_L
.set REG_DMA3CNT_H, REG_BASE + OFFSET_REG_DMA3CNT_H
.set REG_TM0CNT, REG_BASE + OFFSET_REG_TM0CNT
.set REG_TM0CNT_L, REG_BASE + OFFSET_REG_TM0CNT_L
.set REG_TM0CNT_H, REG_BASE + OFFSET_REG_TM0CNT_H
.set REG_TM1CNT, REG_BASE + OFFSET_REG_TM1CNT
.set REG_TM1CNT_L, REG_BASE + OFFSET_REG_TM1CNT_L
.set REG_TM1CNT_H, REG_BASE + OFFSET_REG_TM1CNT_H
.set REG_TM2CNT, REG_BASE + OFFSET_REG_TM2CNT
.set REG_TM2CNT_L, REG_BASE + OFFSET_REG_TM2CNT_L
.set REG_TM2CNT_H, REG_BASE + OFFSET_REG_TM2CNT_H
.set REG_TM3CNT, REG_BASE + OFFSET_REG_TM3CNT
.set REG_TM3CNT_L, REG_BASE + OFFSET_REG_TM3CNT_L
.set REG_TM3CNT_H, REG_BASE + OFFSET_REG_TM3CNT_H
.set REG_SIOCNT, REG_BASE + OFFSET_REG_SIOCNT
.set REG_SIODATA8, REG_BASE + OFFSET_REG_SIODATA8
.set REG_SIODATA32, REG_BASE + OFFSET_REG_SIODATA32
.set REG_SIOMLT_SEND, REG_BASE + OFFSET_REG_SIOMLT_SEND
.set REG_SIOMLT_RECV, REG_BASE + OFFSET_REG_SIOMLT_RECV
.set REG_SIOMULTI0, REG_BASE + OFFSET_REG_SIOMULTI0
.set REG_SIOMULTI1, REG_BASE + OFFSET_REG_SIOMULTI1
.set REG_SIOMULTI2, REG_BASE + OFFSET_REG_SIOMULTI2
.set REG_SIOMULTI3, REG_BASE + OFFSET_REG_SIOMULTI3
.set REG_KEYINPUT, REG_BASE + OFFSET_REG_KEYINPUT
.set REG_KEYCNT, REG_BASE + OFFSET_REG_KEYCNT
.set REG_RCNT, REG_BASE + OFFSET_REG_RCNT
.set REG_JOYCNT, REG_BASE + OFFSET_REG_JOYCNT
.set REG_JOYSTAT, REG_BASE + OFFSET_REG_JOYSTAT
.set REG_JOY_RECV, REG_BASE + OFFSET_REG_JOY_RECV
.set REG_JOY_RECV_L, REG_BASE + OFFSET_REG_JOY_RECV_L
.set REG_JOY_RECV_H, REG_BASE + OFFSET_REG_JOY_RECV_H
.set REG_JOY_TRANS, REG_BASE + OFFSET_REG_JOY_TRANS
.set REG_JOY_TRANS_L, REG_BASE + OFFSET_REG_JOY_TRANS_L
.set REG_JOY_TRANS_H, REG_BASE + OFFSET_REG_JOY_TRANS_H
.set REG_IME, REG_BASE + OFFSET_REG_IME
.set REG_IE, REG_BASE + OFFSET_REG_IE
.set REG_IF, REG_BASE + OFFSET_REG_IF
.set REG_WAITCNT, REG_BASE + OFFSET_REG_WAITCNT
@ DMA register constants
.set DMA_DEST_INC, 0x0000
.set DMA_DEST_DEC, 0x0020
.set DMA_DEST_FIXED, 0x0040
.set DMA_DEST_RELOAD, 0x0060
.set DMA_SRC_INC, 0x0000
.set DMA_SRC_DEC, 0x0080
.set DMA_SRC_FIXED, 0x0100
.set DMA_REPEAT, 0x0200
.set DMA_16BIT, 0x0000
.set DMA_32BIT, 0x0400
.set DMA_DREQ_ON, 0x0800
.set DMA_START_NOW, 0x0000
.set DMA_START_VBLANK, 0x1000
.set DMA_START_HBLANK, 0x2000
.set DMA_START_SPECIAL, 0x3000
.set DMA_INTR_ENABLE, 0x4000
.set DMA_ENABLE, 0x8000
@ OAM attribute constants
.set OAM_OBJ_NORMAL, 0x00000000
.set OAM_OBJ_BLEND, 0x00000400
.set OAM_OBJ_WINDOW, 0x00000800
.set OAM_AFFINE_NONE, 0x00000000
.set OAM_AFFINE_NORMAL_SIZE, 0x00000100
.set OAM_OBJ_DISABLED, 0x00000200
.set OAM_AFFINE_DOUBLE_SIZE, 0x00000300
.set OAM_MOSAIC_OFF, 0x00000000
.set OAM_MOSAIC_ON, 0x00001000
.set OAM_4BPP, 0x00000000
.set OAM_8BPP, 0x00002000
.set OAM_H_FLIP, 0x10000000
.set OAM_V_FLIP, 0x20000000
.set OAM_SQUARE, 0x00000000
.set OAM_H_RECTANGLE, 0x00004000
.set OAM_V_RECTANGLE, 0x00008000
.set OAM_SIZE_0, 0x00000000
.set OAM_SIZE_1, 0x40000000
.set OAM_SIZE_2, 0x80000000
.set OAM_SIZE_3, 0xc0000000
.set OAM_SIZE_8x8, OAM_SIZE_0 | OAM_SQUARE
.set OAM_SIZE_16x16, OAM_SIZE_1 | OAM_SQUARE
.set OAM_SIZE_32x32, OAM_SIZE_2 | OAM_SQUARE
.set OAM_SIZE_64x64, OAM_SIZE_3 | OAM_SQUARE
.set OAM_SIZE_16x8, OAM_SIZE_0 | OAM_H_RECTANGLE
.set OAM_SIZE_32x8, OAM_SIZE_1 | OAM_H_RECTANGLE
.set OAM_SIZE_32x16, OAM_SIZE_2 | OAM_H_RECTANGLE
.set OAM_SIZE_64x32, OAM_SIZE_3 | OAM_H_RECTANGLE
.set OAM_SIZE_8x16, OAM_SIZE_0 | OAM_V_RECTANGLE
.set OAM_SIZE_8x32, OAM_SIZE_1 | OAM_V_RECTANGLE
.set OAM_SIZE_16x32, OAM_SIZE_2 | OAM_V_RECTANGLE
.set OAM_SIZE_32x64, OAM_SIZE_3 | OAM_V_RECTANGLE
@ SIO constants
.set SIO_ENABLE, 0x80
.set SIO_ERROR, 0x40
constants/misc_constants.inc
+19
View File
@@ -0,0 +1,19 @@
.set TRUE, 1
.set FALSE, 0
.set NULL, 0
.set SPRITE_SIZE_8x8, (OAM_SIZE_0 >> 28) | (OAM_SQUARE >> 14)
.set SPRITE_SIZE_16x16, (OAM_SIZE_1 >> 28) | (OAM_SQUARE >> 14)
.set SPRITE_SIZE_32x32, (OAM_SIZE_2 >> 28) | (OAM_SQUARE >> 14)
.set SPRITE_SIZE_64x64, (OAM_SIZE_3 >> 28) | (OAM_SQUARE >> 14)
.set SPRITE_SIZE_16x8, (OAM_SIZE_0 >> 28) | (OAM_H_RECTANGLE >> 14)
.set SPRITE_SIZE_32x8, (OAM_SIZE_1 >> 28) | (OAM_H_RECTANGLE >> 14)
.set SPRITE_SIZE_32x16, (OAM_SIZE_2 >> 28) | (OAM_H_RECTANGLE >> 14)
.set SPRITE_SIZE_64x32, (OAM_SIZE_3 >> 28) | (OAM_H_RECTANGLE >> 14)
.set SPRITE_SIZE_8x16, (OAM_SIZE_0 >> 28) | (OAM_V_RECTANGLE >> 14)
.set SPRITE_SIZE_8x32, (OAM_SIZE_1 >> 28) | (OAM_V_RECTANGLE >> 14)
.set SPRITE_SIZE_16x32, (OAM_SIZE_2 >> 28) | (OAM_V_RECTANGLE >> 14)
.set SPRITE_SIZE_32x64, (OAM_SIZE_3 >> 28) | (OAM_V_RECTANGLE >> 14)
constants/multi_sio_constants.inc
+66
View File
@@ -0,0 +1,66 @@
@ Optimize the following settings based on the software specifications
MULTI_SIO_BLOCK_SIZE = 20 @ Communication Data Block Size (Max. 24 Bytes)
MULTI_SIO_PLAYERS_MAX = 4 @ Maximum Number of Players
MULTI_SIO_SYNC_DATA = 0xfefe @ Synchronized Data (0x0000/0xfffa~0xffff prohibited)
@ Comment out if no space in CPU internal Work RAM
MULTI_SIO_DI_FUNC_FAST = 1 @ SIO Interrupt Prohibit Function High Speed Flag (CPU Internal RAM Execution)
MULTI_SIO_TIMER_NO = 3 @ Timer No.
MULTI_SIO_TIMER_INTR_FLAG = (INTR_FLAG_TIMER0 << MULTI_SIO_TIMER_NO)
@ Timer Interrupt Flag
REG_MULTI_SIO_TIMER = (REG_TM0CNT + MULTI_SIO_TIMER_NO * 4)
REG_MULTI_SIO_TIMER_L = REG_MULTI_SIO_TIMER
REG_MULTI_SIO_TIMER_H = (REG_MULTI_SIO_TIMER + 2)
@ Timer Register
@ Multi-play Communication Packet Structure Offset
OFS_MSP_FRAME_COUNTER = 0 @ Frame Counter
OFS_MSP_RECV_ERROR_FLAGS = 1 @ Receive Error Flag
OFS_MSP_CHECK_SUM = 2 @ Checksum
OFS_MSP_DATA = 4 @ Communication Data
OFS_MSP_OVERRUN_CATCH = (OFS_MSP_DATA + MULTI_SIO_BLOCK_SIZE)
@ Overrun Protect Area
MULTI_SIO_PACKET_SIZE = (OFS_MSP_OVERRUN_CATCH + 4)
@ Structure Size
@ Multi-play Communication Work Area Structure Offset
OFS_MS_TYPE = 0 @ Connection (Master/Slave)
OFS_MS_STATE = 1 @ Communication Function State
OFS_MS_CONNECTED_FLAG = 2 @ Connection History Flag
OFS_MS_RECV_SUCCESS_FLAGS = 3 @ Receive Success Flag
OFS_MS_SYNC_RECV_FLAG = 4 @ Synchronized Data Receive Confirmation Flag
OFS_MS_SYNC_RECV_ADJUST_COUNTER = 8 @ Synchronization Adjustment Counter
OFS_MS_SEND_BUF_COUNTER_INIT = 10 @ Send Buffer Counter Initialization
OFS_MS_SYNC_SEND_FRAME_COUNTER = 11 @ Send Frame Counter
OFS_MS_SYNC_RECV_FRAME_COUNTER = 12 @ Receive Frame Counter
OFS_MS_SEND_BUF_COUNTER = 20 @ Send Buffer Counter
OFS_MS_RECV_BUF_COUNTER = 24 @ Receive Buffer Counter
OFS_MS_NEXT_SEND_BUF_P = 40 @ Send Buffer Pointer
OFS_MS_CURRENT_SEND_BUF_P = 44
OFS_MS_CURRENT_RECV_BUF_P = 48 @ Receive Buffer Pointer
OFS_MS_LAST_RECV_BUF_P = 64
OFS_MS_RECV_CHECK_BUF_P = 80
OFS_MS_SEND_BUF = 96 @ Send Buffer (Double Buffer)
OFS_MS_RECV_BUF = (OFS_MS_SEND_BUF + MULTI_SIO_PACKET_SIZE * 2)
@ Receive Buffer (Triple Buffer)
MULTI_SIO_AREA_SIZE = (OFS_MS_RECV_BUF + MULTI_SIO_PACKET_SIZE * 3 * MULTI_SIO_PLAYERS_MAX)
@ Structure Size
OFS_MS_HARD_ERROR = 9
include/gba.inc
-471
View File
@@ -1,471 +0,0 @@
@-------------------------------------------------------------------------------
@ Program Status Register
@-------------------------------------------------------------------------------
PSR_USR_MODE = 0x00000010
PSR_FIQ_MODE = 0x00000011
PSR_IRQ_MODE = 0x00000012
PSR_SVC_MODE = 0x00000013
PSR_ABT_MODE = 0x00000017
PSR_UND_MODE = 0x0000001B
PSR_SYS_MODE = 0x0000001F
PSR_MODE_MASK = 0x0000001F
PSR_THUMB_BIT = 0x00000020
PSR_FIQ_DISABLE_BIT = 0x00000040
PSR_IRQ_DISABLE_BIT = 0x00000080
@-------------------------------------------------------------------------------
@ Memory
@-------------------------------------------------------------------------------
EWRAM_START = 0x02000000
EWRAM_END = EWRAM_START + 0x40000
IWRAM_START = 0x03000000
IWRAM_END = IWRAM_START + 0x8000
REG_BASE = 0x04000000
PLTT = 0x05000000
BG_PLTT = PLTT
OBJ_PLTT = PLTT + 0x200
VRAM = 0x06000000
BG_VRAM = VRAM
OBJ_VRAM0 = VRAM + 0x10000 @ text-mode BG
OBJ_VRAM1 = VRAM + 0x14000 @ bitmap-mode BG
OAM = 0x07000000
SOUND_INFO_PTR = 0x3007FF0
INTR_CHECK = 0x3007FF8
INTR_VECTOR = 0x3007FFC
ROM = 0x08000000
@-------------------------------------------------------------------------------
@ I/O Register Offsets
@-------------------------------------------------------------------------------
REG_OFFSET_DISPCNT = 0x0
REG_OFFSET_DISPSTAT = 0x4
REG_OFFSET_VCOUNT = 0x6
REG_OFFSET_BG0CNT = 0x8
REG_OFFSET_BG1CNT = 0xa
REG_OFFSET_BG2CNT = 0xc
REG_OFFSET_BG3CNT = 0xe
REG_OFFSET_BG0HOFS = 0x10
REG_OFFSET_BG0VOFS = 0x12
REG_OFFSET_BG1HOFS = 0x14
REG_OFFSET_BG1VOFS = 0x16
REG_OFFSET_BG2HOFS = 0x18
REG_OFFSET_BG2VOFS = 0x1a
REG_OFFSET_BG3HOFS = 0x1c
REG_OFFSET_BG3VOFS = 0x1e
REG_OFFSET_BG2PA = 0x20
REG_OFFSET_BG2PB = 0x22
REG_OFFSET_BG2PC = 0x24
REG_OFFSET_BG2PD = 0x26
REG_OFFSET_BG2X_L = 0x28
REG_OFFSET_BG2X_H = 0x2a
REG_OFFSET_BG2Y_L = 0x2c
REG_OFFSET_BG2Y_H = 0x2e
REG_OFFSET_BG3PA = 0x30
REG_OFFSET_BG3PB = 0x32
REG_OFFSET_BG3PC = 0x34
REG_OFFSET_BG3PD = 0x36
REG_OFFSET_BG3X_L = 0x38
REG_OFFSET_BG3X_H = 0x3a
REG_OFFSET_BG3Y_L = 0x3c
REG_OFFSET_BG3Y_H = 0x3e
REG_OFFSET_WIN0H = 0x40
REG_OFFSET_WIN1H = 0x42
REG_OFFSET_WIN0V = 0x44
REG_OFFSET_WIN1V = 0x46
REG_OFFSET_WININ = 0x48
REG_OFFSET_WINOUT = 0x4a
REG_OFFSET_MOSAIC = 0x4c
REG_OFFSET_BLDCNT = 0x50
REG_OFFSET_BLDALPHA = 0x52
REG_OFFSET_BLDY = 0x54
REG_OFFSET_SOUND1CNT = 0x60
REG_OFFSET_SOUND1CNT_L = 0x60
REG_OFFSET_NR10 = 0x60
REG_OFFSET_SOUND1CNT_H = 0x62
REG_OFFSET_NR11 = 0x62
REG_OFFSET_NR12 = 0x63
REG_OFFSET_SOUND1CNT_X = 0x64
REG_OFFSET_NR13 = 0x64
REG_OFFSET_NR14 = 0x65
REG_OFFSET_SOUND2CNT = 0x68
REG_OFFSET_SOUND2CNT_L = 0x68
REG_OFFSET_NR21 = 0x68
REG_OFFSET_NR22 = 0x69
REG_OFFSET_SOUND2CNT_H = 0x6c
REG_OFFSET_NR23 = 0x6c
REG_OFFSET_NR24 = 0x6d
REG_OFFSET_SOUND3CNT = 0x70
REG_OFFSET_SOUND3CNT_L = 0x70
REG_OFFSET_NR30 = 0x70
REG_OFFSET_SOUND3CNT_H = 0x72
REG_OFFSET_NR31 = 0x72
REG_OFFSET_NR32 = 0x73
REG_OFFSET_SOUND3CNT_X = 0x74
REG_OFFSET_NR33 = 0x74
REG_OFFSET_NR34 = 0x75
REG_OFFSET_SOUND4CNT = 0x78
REG_OFFSET_SOUND4CNT_L = 0x78
REG_OFFSET_NR41 = 0x78
REG_OFFSET_NR42 = 0x79
REG_OFFSET_SOUND4CNT_H = 0x7c
REG_OFFSET_NR43 = 0x7c
REG_OFFSET_NR44 = 0x7d
REG_OFFSET_SOUNDCNT = 0x80
REG_OFFSET_SOUNDCNT_L = 0x80
REG_OFFSET_NR50 = 0x80
REG_OFFSET_NR51 = 0x81
REG_OFFSET_SOUNDCNT_H = 0x82
REG_OFFSET_SOUNDCNT_X = 0x84
REG_OFFSET_NR52 = 0x84
REG_OFFSET_SOUNDBIAS = 0x88
REG_OFFSET_WAVE_RAM = 0x90
REG_OFFSET_WAVE_RAM0 = 0x90
REG_OFFSET_WAVE_RAM0_L = 0x90
REG_OFFSET_WAVE_RAM0_H = 0x92
REG_OFFSET_WAVE_RAM1 = 0x94
REG_OFFSET_WAVE_RAM1_L = 0x94
REG_OFFSET_WAVE_RAM1_H = 0x96
REG_OFFSET_WAVE_RAM2 = 0x98
REG_OFFSET_WAVE_RAM2_L = 0x98
REG_OFFSET_WAVE_RAM2_H = 0x9a
REG_OFFSET_WAVE_RAM3 = 0x9c
REG_OFFSET_WAVE_RAM3_L = 0x9c
REG_OFFSET_WAVE_RAM3_H = 0x9e
REG_OFFSET_FIFO = 0xa0
REG_OFFSET_FIFO_A = 0xa0
REG_OFFSET_FIFO_A_L = 0xa0
REG_OFFSET_FIFO_A_H = 0xa2
REG_OFFSET_FIFO_B = 0xa4
REG_OFFSET_FIFO_B_L = 0xa4
REG_OFFSET_FIFO_B_H = 0xa6
REG_OFFSET_DMA0 = 0xb0
REG_OFFSET_DMA0SAD = 0xb0
REG_OFFSET_DMA0SAD_L = 0xb0
REG_OFFSET_DMA0SAD_H = 0xb2
REG_OFFSET_DMA0DAD = 0xb4
REG_OFFSET_DMA0DAD_L = 0xb4
REG_OFFSET_DMA0DAD_H = 0xb6
REG_OFFSET_DMA0CNT = 0xb8
REG_OFFSET_DMA0CNT_L = 0xb8
REG_OFFSET_DMA0CNT_H = 0xba
REG_OFFSET_DMA1 = 0xbc
REG_OFFSET_DMA1SAD = 0xbc
REG_OFFSET_DMA1SAD_L = 0xbc
REG_OFFSET_DMA1SAD_H = 0xbe
REG_OFFSET_DMA1DAD = 0xc0
REG_OFFSET_DMA1DAD_L = 0xc0
REG_OFFSET_DMA1DAD_H = 0xc2
REG_OFFSET_DMA1CNT = 0xc4
REG_OFFSET_DMA1CNT_L = 0xc4
REG_OFFSET_DMA1CNT_H = 0xc6
REG_OFFSET_DMA2 = 0xc8
REG_OFFSET_DMA2SAD = 0xc8
REG_OFFSET_DMA2SAD_L = 0xc8
REG_OFFSET_DMA2SAD_H = 0xca
REG_OFFSET_DMA2DAD = 0xcc
REG_OFFSET_DMA2DAD_L = 0xcc
REG_OFFSET_DMA2DAD_H = 0xce
REG_OFFSET_DMA2CNT = 0xd0
REG_OFFSET_DMA2CNT_L = 0xd0
REG_OFFSET_DMA2CNT_H = 0xd2
REG_OFFSET_DMA3 = 0xd4
REG_OFFSET_DMA3SAD = 0xd4
REG_OFFSET_DMA3SAD_L = 0xd4
REG_OFFSET_DMA3SAD_H = 0xd6
REG_OFFSET_DMA3DAD = 0xd8
REG_OFFSET_DMA3DAD_L = 0xd8
REG_OFFSET_DMA3DAD_H = 0xda
REG_OFFSET_DMA3CNT = 0xdc
REG_OFFSET_DMA3CNT_L = 0xdc
REG_OFFSET_DMA3CNT_H = 0xde
REG_OFFSET_TM0CNT = 0x100
REG_OFFSET_TM0CNT_L = 0x100
REG_OFFSET_TM0CNT_H = 0x102
REG_OFFSET_TM1CNT = 0x104
REG_OFFSET_TM1CNT_L = 0x104
REG_OFFSET_TM1CNT_H = 0x106
REG_OFFSET_TM2CNT = 0x108
REG_OFFSET_TM2CNT_L = 0x108
REG_OFFSET_TM2CNT_H = 0x10a
REG_OFFSET_TM3CNT = 0x10c
REG_OFFSET_TM3CNT_L = 0x10c
REG_OFFSET_TM3CNT_H = 0x10e
REG_OFFSET_SIOCNT = 0x128
REG_OFFSET_SIODATA8 = 0x12a
REG_OFFSET_SIODATA32 = 0x120
REG_OFFSET_SIOMLT_SEND = 0x12a
REG_OFFSET_SIOMLT_RECV = 0x120
REG_OFFSET_SIOMULTI0 = 0x120
REG_OFFSET_SIOMULTI1 = 0x122
REG_OFFSET_SIOMULTI2 = 0x124
REG_OFFSET_SIOMULTI3 = 0x126
REG_OFFSET_KEYINPUT = 0x130
REG_OFFSET_KEYCNT = 0x132
REG_OFFSET_RCNT = 0x134
REG_OFFSET_JOYCNT = 0x140
REG_OFFSET_JOYSTAT = 0x158
REG_OFFSET_JOY_RECV = 0x150
REG_OFFSET_JOY_RECV_L = 0x150
REG_OFFSET_JOY_RECV_H = 0x152
REG_OFFSET_JOY_TRANS = 0x154
REG_OFFSET_JOY_TRANS_L = 0x154
REG_OFFSET_JOY_TRANS_H = 0x156
REG_OFFSET_IME = 0x208
REG_OFFSET_IE = 0x200
REG_OFFSET_IF = 0x202
REG_OFFSET_WAITCNT = 0x204
@-------------------------------------------------------------------------------
@ I/O Register Addresses
@-------------------------------------------------------------------------------
REG_DISPCNT = (REG_BASE + REG_OFFSET_DISPCNT)
REG_DISPSTAT = (REG_BASE + REG_OFFSET_DISPSTAT)
REG_VCOUNT = (REG_BASE + REG_OFFSET_VCOUNT)
REG_BG0CNT = (REG_BASE + REG_OFFSET_BG0CNT)
REG_BG1CNT = (REG_BASE + REG_OFFSET_BG1CNT)
REG_BG2CNT = (REG_BASE + REG_OFFSET_BG2CNT)
REG_BG3CNT = (REG_BASE + REG_OFFSET_BG3CNT)
REG_BG0HOFS = (REG_BASE + REG_OFFSET_BG0HOFS)
REG_BG0VOFS = (REG_BASE + REG_OFFSET_BG0VOFS)
REG_BG1HOFS = (REG_BASE + REG_OFFSET_BG1HOFS)
REG_BG1VOFS = (REG_BASE + REG_OFFSET_BG1VOFS)
REG_BG2HOFS = (REG_BASE + REG_OFFSET_BG2HOFS)
REG_BG2VOFS = (REG_BASE + REG_OFFSET_BG2VOFS)
REG_BG3HOFS = (REG_BASE + REG_OFFSET_BG3HOFS)
REG_BG3VOFS = (REG_BASE + REG_OFFSET_BG3VOFS)
REG_BG2PA = (REG_BASE + REG_OFFSET_BG2PA)
REG_BG2PB = (REG_BASE + REG_OFFSET_BG2PB)
REG_BG2PC = (REG_BASE + REG_OFFSET_BG2PC)
REG_BG2PD = (REG_BASE + REG_OFFSET_BG2PD)
REG_BG2X_L = (REG_BASE + REG_OFFSET_BG2X_L)
REG_BG2X_H = (REG_BASE + REG_OFFSET_BG2X_H)
REG_BG2Y_L = (REG_BASE + REG_OFFSET_BG2Y_L)
REG_BG2Y_H = (REG_BASE + REG_OFFSET_BG2Y_H)
REG_BG3PA = (REG_BASE + REG_OFFSET_BG3PA)
REG_BG3PB = (REG_BASE + REG_OFFSET_BG3PB)
REG_BG3PC = (REG_BASE + REG_OFFSET_BG3PC)
REG_BG3PD = (REG_BASE + REG_OFFSET_BG3PD)
REG_BG3X_L = (REG_BASE + REG_OFFSET_BG3X_L)
REG_BG3X_H = (REG_BASE + REG_OFFSET_BG3X_H)
REG_BG3Y_L = (REG_BASE + REG_OFFSET_BG3Y_L)
REG_BG3Y_H = (REG_BASE + REG_OFFSET_BG3Y_H)
REG_WIN0H = (REG_BASE + REG_OFFSET_WIN0H)
REG_WIN1H = (REG_BASE + REG_OFFSET_WIN1H)
REG_WIN0V = (REG_BASE + REG_OFFSET_WIN0V)
REG_WIN1V = (REG_BASE + REG_OFFSET_WIN1V)
REG_WININ = (REG_BASE + REG_OFFSET_WININ)
REG_WINOUT = (REG_BASE + REG_OFFSET_WINOUT)
REG_MOSAIC = (REG_BASE + REG_OFFSET_MOSAIC)
REG_BLDCNT = (REG_BASE + REG_OFFSET_BLDCNT)
REG_BLDALPHA = (REG_BASE + REG_OFFSET_BLDALPHA)
REG_BLDY = (REG_BASE + REG_OFFSET_BLDY)
REG_SOUND1CNT = (REG_BASE + REG_OFFSET_SOUND1CNT)
REG_SOUND1CNT_L = (REG_BASE + REG_OFFSET_SOUND1CNT_L)
REG_NR10 = (REG_BASE + REG_OFFSET_NR10)
REG_SOUND1CNT_H = (REG_BASE + REG_OFFSET_SOUND1CNT_H)
REG_NR11 = (REG_BASE + REG_OFFSET_NR11)
REG_NR12 = (REG_BASE + REG_OFFSET_NR12)
REG_SOUND1CNT_X = (REG_BASE + REG_OFFSET_SOUND1CNT_X)
REG_NR13 = (REG_BASE + REG_OFFSET_NR13)
REG_NR14 = (REG_BASE + REG_OFFSET_NR14)
REG_SOUND2CNT = (REG_BASE + REG_OFFSET_SOUND2CNT)
REG_SOUND2CNT_L = (REG_BASE + REG_OFFSET_SOUND2CNT_L)
REG_NR21 = (REG_BASE + REG_OFFSET_NR21)
REG_NR22 = (REG_BASE + REG_OFFSET_NR22)
REG_SOUND2CNT_H = (REG_BASE + REG_OFFSET_SOUND2CNT_H)
REG_NR23 = (REG_BASE + REG_OFFSET_NR23)
REG_NR24 = (REG_BASE + REG_OFFSET_NR24)
REG_SOUND3CNT = (REG_BASE + REG_OFFSET_SOUND3CNT)
REG_SOUND3CNT_L = (REG_BASE + REG_OFFSET_SOUND3CNT_L)
REG_NR30 = (REG_BASE + REG_OFFSET_NR30)
REG_SOUND3CNT_H = (REG_BASE + REG_OFFSET_SOUND3CNT_H)
REG_NR31 = (REG_BASE + REG_OFFSET_NR31)
REG_NR32 = (REG_BASE + REG_OFFSET_NR32)
REG_SOUND3CNT_X = (REG_BASE + REG_OFFSET_SOUND3CNT_X)
REG_NR33 = (REG_BASE + REG_OFFSET_NR33)
REG_NR34 = (REG_BASE + REG_OFFSET_NR34)
REG_SOUND4CNT = (REG_BASE + REG_OFFSET_SOUND4CNT)
REG_SOUND4CNT_L = (REG_BASE + REG_OFFSET_SOUND4CNT_L)
REG_NR41 = (REG_BASE + REG_OFFSET_NR41)
REG_NR42 = (REG_BASE + REG_OFFSET_NR42)
REG_SOUND4CNT_H = (REG_BASE + REG_OFFSET_SOUND4CNT_H)
REG_NR43 = (REG_BASE + REG_OFFSET_NR43)
REG_NR44 = (REG_BASE + REG_OFFSET_NR44)
REG_SOUNDCNT = (REG_BASE + REG_OFFSET_SOUNDCNT)
REG_SOUNDCNT_L = (REG_BASE + REG_OFFSET_SOUNDCNT_L)
REG_NR50 = (REG_BASE + REG_OFFSET_NR50)
REG_NR51 = (REG_BASE + REG_OFFSET_NR51)
REG_SOUNDCNT_H = (REG_BASE + REG_OFFSET_SOUNDCNT_H)
REG_SOUNDCNT_X = (REG_BASE + REG_OFFSET_SOUNDCNT_X)
REG_NR52 = (REG_BASE + REG_OFFSET_NR52)
REG_SOUNDBIAS = (REG_BASE + REG_OFFSET_SOUNDBIAS)
REG_WAVE_RAM = (REG_BASE + REG_OFFSET_WAVE_RAM)
REG_WAVE_RAM0 = (REG_BASE + REG_OFFSET_WAVE_RAM0)
REG_WAVE_RAM0_L = (REG_BASE + REG_OFFSET_WAVE_RAM0_L)
REG_WAVE_RAM0_H = (REG_BASE + REG_OFFSET_WAVE_RAM0_H)
REG_WAVE_RAM1 = (REG_BASE + REG_OFFSET_WAVE_RAM1)
REG_WAVE_RAM1_L = (REG_BASE + REG_OFFSET_WAVE_RAM1_L)
REG_WAVE_RAM1_H = (REG_BASE + REG_OFFSET_WAVE_RAM1_H)
REG_WAVE_RAM2 = (REG_BASE + REG_OFFSET_WAVE_RAM2)
REG_WAVE_RAM2_L = (REG_BASE + REG_OFFSET_WAVE_RAM2_L)
REG_WAVE_RAM2_H = (REG_BASE + REG_OFFSET_WAVE_RAM2_H)
REG_WAVE_RAM3 = (REG_BASE + REG_OFFSET_WAVE_RAM3)
REG_WAVE_RAM3_L = (REG_BASE + REG_OFFSET_WAVE_RAM3_L)
REG_WAVE_RAM3_H = (REG_BASE + REG_OFFSET_WAVE_RAM3_H)
REG_FIFO = (REG_BASE + REG_OFFSET_FIFO)
REG_FIFO_A = (REG_BASE + REG_OFFSET_FIFO_A)
REG_FIFO_A_L = (REG_BASE + REG_OFFSET_FIFO_A_L)
REG_FIFO_A_H = (REG_BASE + REG_OFFSET_FIFO_A_H)
REG_FIFO_B = (REG_BASE + REG_OFFSET_FIFO_B)
REG_FIFO_B_L = (REG_BASE + REG_OFFSET_FIFO_B_L)
REG_FIFO_B_H = (REG_BASE + REG_OFFSET_FIFO_B_H)
REG_DMA0 = (REG_BASE + REG_OFFSET_DMA0)
REG_DMA0SAD = (REG_BASE + REG_OFFSET_DMA0SAD)
REG_DMA0SAD_L = (REG_BASE + REG_OFFSET_DMA0SAD_L)
REG_DMA0SAD_H = (REG_BASE + REG_OFFSET_DMA0SAD_H)
REG_DMA0DAD = (REG_BASE + REG_OFFSET_DMA0DAD)
REG_DMA0DAD_L = (REG_BASE + REG_OFFSET_DMA0DAD_L)
REG_DMA0DAD_H = (REG_BASE + REG_OFFSET_DMA0DAD_H)
REG_DMA0CNT = (REG_BASE + REG_OFFSET_DMA0CNT)
REG_DMA0CNT_L = (REG_BASE + REG_OFFSET_DMA0CNT_L)
REG_DMA0CNT_H = (REG_BASE + REG_OFFSET_DMA0CNT_H)
REG_DMA1 = (REG_BASE + REG_OFFSET_DMA1)
REG_DMA1SAD = (REG_BASE + REG_OFFSET_DMA1SAD)
REG_DMA1SAD_L = (REG_BASE + REG_OFFSET_DMA1SAD_L)
REG_DMA1SAD_H = (REG_BASE + REG_OFFSET_DMA1SAD_H)
REG_DMA1DAD = (REG_BASE + REG_OFFSET_DMA1DAD)
REG_DMA1DAD_L = (REG_BASE + REG_OFFSET_DMA1DAD_L)
REG_DMA1DAD_H = (REG_BASE + REG_OFFSET_DMA1DAD_H)
REG_DMA1CNT = (REG_BASE + REG_OFFSET_DMA1CNT)
REG_DMA1CNT_L = (REG_BASE + REG_OFFSET_DMA1CNT_L)
REG_DMA1CNT_H = (REG_BASE + REG_OFFSET_DMA1CNT_H)
REG_DMA2 = (REG_BASE + REG_OFFSET_DMA2)
REG_DMA2SAD = (REG_BASE + REG_OFFSET_DMA2SAD)
REG_DMA2SAD_L = (REG_BASE + REG_OFFSET_DMA2SAD_L)
REG_DMA2SAD_H = (REG_BASE + REG_OFFSET_DMA2SAD_H)
REG_DMA2DAD = (REG_BASE + REG_OFFSET_DMA2DAD)
REG_DMA2DAD_L = (REG_BASE + REG_OFFSET_DMA2DAD_L)
REG_DMA2DAD_H = (REG_BASE + REG_OFFSET_DMA2DAD_H)
REG_DMA2CNT = (REG_BASE + REG_OFFSET_DMA2CNT)
REG_DMA2CNT_L = (REG_BASE + REG_OFFSET_DMA2CNT_L)
REG_DMA2CNT_H = (REG_BASE + REG_OFFSET_DMA2CNT_H)
REG_DMA3 = (REG_BASE + REG_OFFSET_DMA3)
REG_DMA3SAD = (REG_BASE + REG_OFFSET_DMA3SAD)
REG_DMA3SAD_L = (REG_BASE + REG_OFFSET_DMA3SAD_L)
REG_DMA3SAD_H = (REG_BASE + REG_OFFSET_DMA3SAD_H)
REG_DMA3DAD = (REG_BASE + REG_OFFSET_DMA3DAD)
REG_DMA3DAD_L = (REG_BASE + REG_OFFSET_DMA3DAD_L)
REG_DMA3DAD_H = (REG_BASE + REG_OFFSET_DMA3DAD_H)
REG_DMA3CNT = (REG_BASE + REG_OFFSET_DMA3CNT)
REG_DMA3CNT_L = (REG_BASE + REG_OFFSET_DMA3CNT_L)
REG_DMA3CNT_H = (REG_BASE + REG_OFFSET_DMA3CNT_H)
REG_TM0CNT = (REG_BASE + REG_OFFSET_TM0CNT)
REG_TM0CNT_L = (REG_BASE + REG_OFFSET_TM0CNT_L)
REG_TM0CNT_H = (REG_BASE + REG_OFFSET_TM0CNT_H)
REG_TM1CNT = (REG_BASE + REG_OFFSET_TM1CNT)
REG_TM1CNT_L = (REG_BASE + REG_OFFSET_TM1CNT_L)
REG_TM1CNT_H = (REG_BASE + REG_OFFSET_TM1CNT_H)
REG_TM2CNT = (REG_BASE + REG_OFFSET_TM2CNT)
REG_TM2CNT_L = (REG_BASE + REG_OFFSET_TM2CNT_L)
REG_TM2CNT_H = (REG_BASE + REG_OFFSET_TM2CNT_H)
REG_TM3CNT = (REG_BASE + REG_OFFSET_TM3CNT)
REG_TM3CNT_L = (REG_BASE + REG_OFFSET_TM3CNT_L)
REG_TM3CNT_H = (REG_BASE + REG_OFFSET_TM3CNT_H)
REG_SIOCNT = (REG_BASE + REG_OFFSET_SIOCNT)
REG_SIODATA8 = (REG_BASE + REG_OFFSET_SIODATA8)
REG_SIODATA32 = (REG_BASE + REG_OFFSET_SIODATA32)
REG_SIOMLT_SEND = (REG_BASE + REG_OFFSET_SIOMLT_SEND)
REG_SIOMLT_RECV = (REG_BASE + REG_OFFSET_SIOMLT_RECV)
REG_SIOMULTI0 = (REG_BASE + REG_OFFSET_SIOMULTI0)
REG_SIOMULTI1 = (REG_BASE + REG_OFFSET_SIOMULTI1)
REG_SIOMULTI2 = (REG_BASE + REG_OFFSET_SIOMULTI2)
REG_SIOMULTI3 = (REG_BASE + REG_OFFSET_SIOMULTI3)
REG_KEYINPUT = (REG_BASE + REG_OFFSET_KEYINPUT)
REG_KEYCNT = (REG_BASE + REG_OFFSET_KEYCNT)
REG_RCNT = (REG_BASE + REG_OFFSET_RCNT)
REG_JOYCNT = (REG_BASE + REG_OFFSET_JOYCNT)
REG_JOYSTAT = (REG_BASE + REG_OFFSET_JOYSTAT)
REG_JOY_RECV = (REG_BASE + REG_OFFSET_JOY_RECV)
REG_JOY_RECV_L = (REG_BASE + REG_OFFSET_JOY_RECV_L)
REG_JOY_RECV_H = (REG_BASE + REG_OFFSET_JOY_RECV_H)
REG_JOY_TRANS = (REG_BASE + REG_OFFSET_JOY_TRANS)
REG_JOY_TRANS_L = (REG_BASE + REG_OFFSET_JOY_TRANS_L)
REG_JOY_TRANS_H = (REG_BASE + REG_OFFSET_JOY_TRANS_H)
REG_IME = (REG_BASE + REG_OFFSET_IME)
REG_IE = (REG_BASE + REG_OFFSET_IE)
REG_IF = (REG_BASE + REG_OFFSET_IF)
REG_WAITCNT = (REG_BASE + REG_OFFSET_WAITCNT)
@-------------------------------------------------------------------------------
@ I/O Register Flags
@-------------------------------------------------------------------------------
@ DMA
DMA_DEST_INC = 0x0000
DMA_DEST_DEC = 0x0020
DMA_DEST_FIXED = 0x0040
DMA_DEST_RELOAD = 0x0060
DMA_SRC_INC = 0x0000
DMA_SRC_DEC = 0x0080
DMA_SRC_FIXED = 0x0100
DMA_REPEAT = 0x0200
DMA_16BIT = 0x0000
DMA_32BIT = 0x0400
DMA_DREQ_ON = 0x0800
DMA_START_NOW = 0x0000
DMA_START_VBLANK = 0x1000
DMA_START_HBLANK = 0x2000
DMA_START_SPECIAL = 0x3000
DMA_START_MASK = 0x3000
DMA_INTR_ENABLE = 0x4000
DMA_ENABLE = 0x8000
@ Interrupt Flags
INTR_FLAG_VBLANK = (1 << 0)
INTR_FLAG_HBLANK = (1 << 1)
INTR_FLAG_VCOUNT = (1 << 2)
INTR_FLAG_TIMER0 = (1 << 3)
INTR_FLAG_TIMER1 = (1 << 4)
INTR_FLAG_TIMER2 = (1 << 5)
INTR_FLAG_TIMER3 = (1 << 6)
INTR_FLAG_SERIAL = (1 << 7)
INTR_FLAG_DMA0 = (1 << 8)
INTR_FLAG_DMA1 = (1 << 9)
INTR_FLAG_DMA2 = (1 << 10)
INTR_FLAG_DMA3 = (1 << 11)
INTR_FLAG_KEYPAD = (1 << 12)
INTR_FLAG_GAMEPAK = (1 << 13)
VCOUNT_VBLANK = 160
TOTAL_SCANLINES = 228
include/gba/types.h
+133 -87
View File
@@ -28,83 +28,18 @@ typedef u8 bool8;
typedef u16 bool16;
typedef u32 bool32;
struct DispCnt
{
u16 mode:3;
u16 cgbMode:1; // reserved, do not use
u16 bmpFrameNum:1;
u16 hblankIntervalFree:1;
u16 obj1dMap:1;
u16 forcedBlank:1;
u16 bg0_on:1;
u16 bg1_on:1;
u16 bg2_on:1;
u16 bg3_on:1;
u16 obj_on:1;
u16 win0_on:1;
u16 win1_on:1;
u16 objWin_on:1;
};
struct DispStat
{
u16 vblankFlag:1;
u16 hblankFlag:1;
u16 vcountFlag:1;
u16 vblankIrqEnable:1;
u16 hblankIrqEnable:1;
u16 vcountIrqEnable:1;
u16 dummy:2;
u8 vcountCompare;
};
struct BgCnt
{
u16 priority:2;
u16 charBaseBlock:2;
u16 dummy:2;
u16 mosaic:1;
u16 colorMode:1;
u16 palettes:1;
u16 screenBaseBlock:5;
u16 areaOverflowMode:1;
u16 screenSize:2;
};
struct WinCnt
{
u8 win0_bg0_on:1;
u8 win0_bg1_on:1;
u8 win0_bg2_on:1;
u8 win0_bg3_on:1;
u8 win0_obj_on:1;
u8 win0_blend_on:1;
u8 dummy1:2;
u8 win1_bg0_on:1;
u8 win1_bg1_on:1;
u8 win1_bg2_on:1;
u8 win1_bg3_on:1;
u8 win1_obj_on:1;
u8 win1_blend_on:1;
u8 dummy2:2;
};
struct BlendCnt
{
u16 target1_bg0_on:1;
u16 target1_bg1_on:1;
u16 target1_bg2_on:1;
u16 target1_bg3_on:1;
u16 target1_obj_on:1;
u16 target1_bd_on:1;
u16 effect:2;
u16 target2_bg0_on:1;
u16 target2_bg1_on:1;
u16 target2_bg2_on:1;
u16 target2_bg3_on:1;
u16 target2_obj_on:1;
u16 target2_bd_on:1;
};
typedef volatile struct BgCnt vBgCnt;
struct PlttData
{
@@ -112,7 +47,7 @@ struct PlttData
u16 g:5; // green
u16 b:5; // blue
u16 unused_15:1;
} /*__attribute__((packed))*/;
};
typedef union {
struct {
@@ -144,6 +79,10 @@ typedef union {
} all;
} OamData;
#define ST_OAM_HFLIP 0x08
#define ST_OAM_VFLIP 0x10
#define ST_OAM_MNUM_FLIP_MASK 0x18
#define ST_OAM_OBJ_NORMAL 0
#define ST_OAM_OBJ_BLEND 1
#define ST_OAM_OBJ_WINDOW 2
@@ -163,6 +102,29 @@ typedef union {
#define ST_OAM_H_RECTANGLE 1
#define ST_OAM_V_RECTANGLE 2
#define ST_OAM_SIZE_0 0
#define ST_OAM_SIZE_1 1
#define ST_OAM_SIZE_2 2
#define ST_OAM_SIZE_3 3
#define SPRITE_SIZE_8x8 ((ST_OAM_SIZE_0 << 2) | (ST_OAM_SQUARE))
#define SPRITE_SIZE_16x16 ((ST_OAM_SIZE_1 << 2) | (ST_OAM_SQUARE))
#define SPRITE_SIZE_32x32 ((ST_OAM_SIZE_2 << 2) | (ST_OAM_SQUARE))
#define SPRITE_SIZE_64x64 ((ST_OAM_SIZE_3 << 2) | (ST_OAM_SQUARE))
#define SPRITE_SIZE_16x8 ((ST_OAM_SIZE_0 << 2) | (ST_OAM_H_RECTANGLE))
#define SPRITE_SIZE_32x8 ((ST_OAM_SIZE_1 << 2) | (ST_OAM_H_RECTANGLE))
#define SPRITE_SIZE_32x16 ((ST_OAM_SIZE_2 << 2) | (ST_OAM_H_RECTANGLE))
#define SPRITE_SIZE_64x32 ((ST_OAM_SIZE_3 << 2) | (ST_OAM_H_RECTANGLE))
#define SPRITE_SIZE_8x16 ((ST_OAM_SIZE_0 << 2) | (ST_OAM_V_RECTANGLE))
#define SPRITE_SIZE_8x32 ((ST_OAM_SIZE_1 << 2) | (ST_OAM_V_RECTANGLE))
#define SPRITE_SIZE_16x32 ((ST_OAM_SIZE_2 << 2) | (ST_OAM_V_RECTANGLE))
#define SPRITE_SIZE_32x64 ((ST_OAM_SIZE_3 << 2) | (ST_OAM_V_RECTANGLE))
#define SPRITE_SIZE(dim) ((SPRITE_SIZE_##dim >> 2) & 0x03)
#define SPRITE_SHAPE(dim) (SPRITE_SIZE_##dim & 0x03)
struct BgAffineSrcData
{
s32 texX;
@@ -191,6 +153,31 @@ struct ObjAffineSrcData
u16 rotation;
};
// Normal SIO Control Structure
struct SioNormalCnt
{
u16 sck_I_O:1; // Clock I/O Select
u16 sck:1; // Internal Clock Select
u16 ackRecv:1; // Transfer Enable Flag Receive
u16 ackSend:1; // Transfer Enable Flag Send
u16 unused_6_4:3;
u16 enable:1; // SIO Enable
u16 unused_11_8:4;
u16 mode:2; // Communication Mode Select
u16 ifEnable:1; // Interrupt Request Enable
u16 unused_15:1;
u8 data; // Data
u8 unused_31_24;
};
#define ST_SIO_8BIT_MODE 0 // Normal 8-bit communication mode
#define ST_SIO_32BIT_MODE 1 // Normal 32-bit communication mode
#define ST_SIO_SCK_OUT 0 // Select external clock
#define ST_SIO_SCK_IN 1 // Select internal clock
#define ST_SIO_IN_SCK_256K 0 // Select internal clock 256KHz
#define ST_SIO_IN_SCK_2M 1 // Select 2MHz
// Multi-player SIO Control Structure
struct SioMultiCnt
{
@@ -202,32 +189,91 @@ struct SioMultiCnt
u16 enable:1; // SIO enable
u16 unused_11_8:4;
u16 mode:2; // communication mode (should equal 2)
u16 intrEnable:1; // IRQ enable
u16 ifEnable:1; // IRQ enable
u16 unused_15:1;
u16 data; // data
};
#define ST_SIO_MULTI_MODE 2 // Multi-player communication mode
#define ST_SIO_MULTI_MODE 2 // Multi-play communication mode
// baud rate
#define ST_SIO_9600_BPS 0 // 9600 bps
#define ST_SIO_38400_BPS 1 // 38400 bps
#define ST_SIO_57600_BPS 2 // 57600 bps
#define ST_SIO_115200_BPS 3 // 115200 bps
#define ST_SIO_9600_BPS 0 // Baud rate 9600 bps
#define ST_SIO_38400_BPS 1 // 38400 bps
#define ST_SIO_57600_BPS 2 // 57600 bps
#define ST_SIO_115200_BPS 3 // 115200 bps
#define ST_SIO_MULTI_PARENT 1 // Multi-play communication Connect master
#define ST_SIO_MULTI_CHILD 0 // Connect slave
struct WaitCnt
// UART - SIO Control Structure
struct SioUartCnt
{
u16 sramWait:2;
u16 rom0_1stAcc:2;
u16 rom0_2ndAcc:1;
u16 rom1_1stAcc:2;
u16 rom1_2ndAcc:1;
u16 rom2_1stAcc:2;
u16 rom2_2ndAcc:1;
u16 phiTerminalClock:2;
u16 dummy:1;
u16 prefetchBufEnable:1;
u16 gamePakType:1;
u16 baudRate:2; // Baud Rate
u16 ctsEnable:1; // Send Signal Enable
u16 paritySelect:1; // Parity Even/Odd
u16 transDataFull:1; // Transmit Data Full
u16 recvDataEmpty:1; // Receive Data Empty
u16 error:1; // Error Detect
u16 length:1; // Data Length
u16 fifoEnable:1; // FIFO Enable
u16 parityEnable:1; // Parity Enable
u16 transEnable:1; // Transmitter Enable
u16 recvEnable:1; // Receiver Enable
u16 mode:2; // Communication Mode Select
u16 ifEnable:1; // Interrupt Request Enable
u16 unused_15:1;
u8 data; // Data
u8 unused_31_24;
};
#define ST_SIO_UART_MODE 3 // UART communication mode
#define ST_SIO_UART_7BIT 0 // UART communication data length 7 bits
#define ST_SIO_UART_8BIT 1 // 8 bits
#define ST_SIO_PARITY_EVEN 0 // Even parity
#define ST_SIO_PARITY_ODD 1 // Odd parity
// JOY Bus Communication Control Structure
struct JoyCnt
{
u8 ifReset:1; // JOY Bus Reset Interrupt Request
u8 ifRecv:1; // JOY Bus Received Interrupt Request
u8 ifSend:1; // JOY Bus Sent Interrupt Request
u8 unused_5_3:3;
u8 ifEnable:1; // Interrupt Request Enable
u8 unused_7:1;
};
// JOY Bus Communication Status Structure
struct JoyStat
{
u8 unused_0:1;
u8 recv:1; // Receive Status
u8 unused_2:1;
u8 send:1; // Send Status
u8 flags:2; // General Flag
u8 unused_7_6:2;
};
// General Input/Output Control Structure
struct RCnt
{
u8 sc:1; // Data
u8 sd:1;
u8 si:1;
u8 so:1;
u8 sc_i_o:1; // I/O Select
u8 sd_i_o:1;
u8 si_i_o:1;
u8 so_i_o:1;
u8 ifEnable:1; // Interrupt Request Enable
u8 unused_13_9:5;
u8 sioModeMaster:2; // SIO Mode Master
};
#define ST_R_SIO_MASTER_MODE 0 // SIO master mode
#define ST_R_DIRECT_MODE 2 // General input/output communication mode
#define ST_R_JOY_MODE 3 // JOY communication mode
#define ST_R_IN 0 // Select input
#define ST_R_OUT 1 // Select output
#endif // GUARD_GBA_TYPES_H
include/multi_sio.h
+1 -1
View File
@@ -125,7 +125,7 @@ struct MultiSioArea
};
extern u32 gMultiSioRecvFuncBuf[0x40 / 4]; // Receive Data/Check Buffer Change Routine RAM Execution Buffer
extern u32 gMultiSioIntrFuncBuf[0x180 / 4]; // Interrupt Routine RAM Execution Buffer
extern u32 gMultiSioIntrFuncBuf[0x120 / 4]; // Interrupt Routine RAM Execution Buffer
extern struct MultiSioArea gMultiSioArea; // Multi-play Communication Work Area
ldscript.txt
+3 -1
View File
@@ -23,7 +23,9 @@ SECTIONS
ALIGN(4)
{
build/sa2/asm/crt0.o(.text);
build/sa2/asm/libraries.o(.text);
build/sa2/asm/multi_sio_asm.o(.text);
build/sa2/src/multi_sio.o(.text);
build/sa2/asm/libraries1.o(.text);
build/sa2/src/main.o(.text);
build/sa2/src/task.o(.text);
build/sa2/asm/code0.o(.text);
src/multi_sio.c
+42
View File
@@ -1,3 +1,45 @@
#include "global.h"
#include "multi_sio.h"
static const char sMultiSioLibVer[] = "MultiSio4Sio32Load010528";
#ifdef MULTI_SIO_DI_FUNC_FAST
// u32 gMultiSioRecvFuncBuf[0x40 / 4]; // Receive Data/Check Buffer Change Routine RAM Execution Buffer
// u32 gMultiSioIntrFuncBuf[0x180 / 4]; // Interrupt Routine RAM Execution Buffer
#endif
/*------------------------------------------------------------------*/
/* Multi-play Communication Initialization */
/*------------------------------------------------------------------*/
extern u32 MultiSioRecvBufChange(void);
void MultiSioInit(u32 connectedFlags)
{
s32 i;
REG_IME = 0;
REG_IE &= ~(INTR_FLAG_SERIAL // Disable SIO & Timer Interrupt
| MULTI_SIO_TIMER_INTR_FLAG);
REG_IME = 1;
REG_RCNT = ST_R_SIO_MASTER_MODE;
*(vu32 *)REG_ADDR_SIOCNT = SIO_MULTI_MODE;
REG_SIOCNT |= SIO_INTR_ENABLE | MULTI_SIO_BAUD_RATE_NO;
CpuFill32(0, &gMultiSioArea, sizeof(struct MultiSioArea)); // Clear Multi-play Communication Work Area
#ifdef MULTI_SIO_DI_FUNC_FAST // Copy Function
CpuCopy32(MultiSioRecvBufChange, gMultiSioRecvFuncBuf, sizeof(gMultiSioRecvFuncBuf));
CpuCopy32(MultiSioIntr, gMultiSioIntrFuncBuf, sizeof(gMultiSioIntrFuncBuf));
#endif
gMultiSioArea.connectedFlags = connectedFlags;
gMultiSioArea.sendBufCounter = 13;
gMultiSioArea.nextSendBufp = (u16 *)&gMultiSioArea.sendBuf[0]; // Set Send Buffer Pointer
gMultiSioArea.currentSendBufp = (u16 *)&gMultiSioArea.sendBuf[1];
for (i = 0; i < 4; ++i)
{ // Set Receive Buffer Pointer
gMultiSioArea.currentRecvBufp[i] = (u16 *)&gMultiSioArea.recvBuf[i][0];
gMultiSioArea.lastRecvBufp[i] = (u16 *)&gMultiSioArea.recvBuf[i][1];
gMultiSioArea.recvCheckBufp[i] = (u16 *)&gMultiSioArea.recvBuf[i][2];
}
REG_IME = 0;
REG_IE |= INTR_FLAG_SERIAL; // Enable SIO Interrupt
REG_IME = 1;
}
sym_iwram.txt
+2 -2
View File
@@ -405,7 +405,7 @@
. = 0x0000051C; gUnknown_0300051C = .;
. = 0x0000051E; gUnknown_0300051E = .;
. = 0x00000558; gUnknown_03000558 = .;
. = 0x00000560; gUnknown_03000560 = .;
. = 0x00000560; gMultiSioArea = .;
. = 0x00000594; gUnknown_03000594 = .;
. = 0x00000598; gUnknown_03000598 = .;
. = 0x0000059C; gUnknown_0300059C = .;
@@ -449,7 +449,7 @@
. = 0x00000711; gUnknown_03000711 = .;
. = 0x00000712; gUnknown_03000712 = .;
. = 0x00000718; gUnknown_03000718 = .;
. = 0x00000750; gUnknown_03000750 = .;
. = 0x00000750; gMultiSioRecvFuncBuf = .;
. = 0x00000758; gUnknown_03000758 = .;
. = 0x00000774; gUnknown_03000774 = .;
. = 0x00000780; gUnknown_03000780 = .;